IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 51

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IDT82P5088BBG

Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82P5088BBG

Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

Available stocks

Company
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Manufacturer
Quantity
Price
Part Number:
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Part Number:
IDT82P5088BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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Part Number:
IDT82P5088BBG
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Quantity:
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Table-52 MAINT4: Maintenance Function Control Register 4
Table-53 MAINT5: Maintenance Function Control Register 5
Table-54 MAINT6: Maintenance Function Control Register 6
PROGRAMMING INFORMATION
IDT82P5088
ERR_SEL[1:0]
RNLPD[7:0]
CNT_STOP
RNLPA[7:0]
EXZ_DEF
ERR_INS
BPV_INS
CNT_MD
Symbol
Symbol
Symbol
-
(R/W, Address = X2FH)
(R/W, Address =X30H)
(R/W, Address = X31H)
7-0
7-0
3-2
Bit
Bit
Bit
7
6
5
4
1
0
(000)00001 Defines the user-programmable receive Inband Loopback activate code. The default selection is 00001.
(00)001001 Defines the user-programmable receive Inband Loopback deactivate code. The default selection is 001001.
Default
Default
Default
00
0
0
0
0
0
0
RNLPA[7:0] form the 8-bit repeating code
RNLPA[6:0] form the 7-bit repeating code
RNLPA[5:0] form the 6-bit repeating code
RNLPA[4:0] form the 5-bit repeating code
RNLPD[7:0] form the 8-bit repeating code
RNLPD[6:0] form the 7-bit repeating code
RNLPD[5:0] form the 6-bit repeating code
RNLPD[4:0] form the 5-bit repeating code
Reserved.
BPV error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single bipolar violation error to be inserted into the transmit data
stream. This bit must be cleared and set again for a subsequent error to be inserted.
PRBS/QRSS logic error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single PRBS/QRSS logic error to be inserted into the transmit PRBS/
QRSS data stream. This bit must be cleared and set again for subsequent error to be inserted.
EXZ definition select
= 0: ANSI
= 1: FCC
These bits choose which type of error will be counted
= 00: the PRBS logic error is counted by a 16-bit error counter.
= 01: the EXZ error is counted by a 16-bit error counter.
= 10: the Received CV (BPV) error is counted by a 16-bit error counter.
= 11: both CV (BPV) and EXZ errors are counted by a 16-bit error counter.
Counter operation mode select
= 0: Manual Report Mode
= 1: Auto Report Mode
= 0: Enable counter.
= 1: Counter is latched.
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
51
Description
Description
Description
February 5, 2009

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