IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 6

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

Table-1
Table-2
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Table-6
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Table-8
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Table-12
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Table-36
List Of Tables
IDT82P5088
Pin Description .............................................................................................................. 10
Transmit Waveform Value For E1 75 W ....................................................................... 19
Transmit Waveform Value For E1 120 W ..................................................................... 19
Transmit Waveform Value For T1 0~133 ft................................................................... 19
Transmit Waveform Value For T1 133~266 ft............................................................... 19
Transmit Waveform Value For T1 266~399 ft............................................................... 20
Transmit Waveform Value For T1 399~533 ft............................................................... 20
Transmit Waveform Value For T1 533~655 ft............................................................... 20
Transmit Waveform Value For J1 0~655 ft ................................................................... 20
Transmit Waveform Value For DS1 0 dB LBO.............................................................. 21
Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 21
Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 21
Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 21
Impedance Matching for Transmitter ............................................................................ 22
Related Bit / Register In Chapter 3.2.6 ......................................................................... 23
Impedance Matching for Receiver ................................................................................ 24
Criteria Of Speed Adjustment Start............................................................................... 27
Related Bit / Register In Chapter 3.3.11 ....................................................................... 27
LOS Declare and Clear Criteria for Short Haul Mode ................................................... 28
LOS Declare and Clear Criteria for Long Haul Mode.................................................... 29
AIS Condition ................................................................................................................ 30
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 30
EXZ Definition ............................................................................................................... 34
Reference Clock Selection............................................................................................ 36
Parallel Microprocessor Interface.................................................................................. 37
Interrupt Event............................................................................................................... 38
Global Register List and Map........................................................................................ 40
Per Channel Register List and Map .............................................................................. 41
ID: Chip Revision Register ............................................................................................ 42
RST: Reset Register ..................................................................................................... 42
MON: G.772 Monitor control Register........................................................................... 42
GPIO: General Purpose IO Pin Definition Register....................................................... 42
REFOUT: Reference clock output select Register........................................................ 43
INTCH: Interrupt Channel Indication Register............................................................... 43
TIMER INTE: Timer Interrupt Enable Register.............................................................. 43
TIMER INTS: Timer Interrupt Status Register............................................................... 44
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
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List Of Tables
February 5, 2009