IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 59

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

Table-64 INTS1: Interrupt Status Register 1
4.3.10 COUNTER REGISTERS
Table-65 CNTL: Error Counter L-byte Register 0
Table-66 CNTH: Error Counter H-byte Register 1
Table-67 REFC: E1 Reference Clock Output Control
PROGRAMMING INFORMATION
IDT82P5088
REFH_LOS:
CNT_H[7:0]
CNT_L[7:0]
CNTOV_IS
Symbol
DAC_IS
ERR_IS
Symbol
Symbol
Symbol
RJA_IS
EXZ_IS
TJA_IS
CV_IS
-
-
(This register is cleared if a ’1’ is written to it.) (R/W, Address = X3BH)
(R, Address = X3D)
(R/W, Address = X3E)
(R, Address = X3CH)
7-0
7-0
7-6
Bit
Bit
Bit
Bit
4
2
1
0
7
6
5
3
0
Default
Default
Default
Default
000000
00H
00H
0
0
0
0
0
0
0
0
0
Reserved
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.
= 0: no pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: no JA overflow interrupt event occurred
= 1: A overflow interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: no JA underflow interrupt event occurred
= 1: JA underflow interrupt event occurred
This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: no PRBS logic error has been received since last reset ERR_IS
= 1: PRBS/QRSS logic error interrupt event occurred
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: no excessive zeros has been received since last reset. EXZ_IS
= 1: EXZ interrupt event occurred
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: no code violation is received since last reset CV_IS
= 1: code violation has received and generate an interrupt request if no masked
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: counter is not over since last reset CNTOV_IS
= 1: counter is over and generate an interrupt request if no masked
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
Reserved
In case of LOS, this bit determines the outputs on the REFA_OUT and REFB_OUT pins.
= 0: Output MCLK.
= 1: Output high level.
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
59
Description
Description
Description
Description
February 5, 2009