IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 26

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

3.3.10 G.772 NON-INTRUSIVE MONITORING
to monitor the data received or transmitted in any one of the remaining chan-
nels. The MON[3:0] bits (MON, 05H) determine which channel and which
direction (transmit/receive) will be monitored. The monitoring is non-intru-
sive per ITU-T G.772.
3.3.11 RECEIVE JITTER ATTENUATOR
or not. This selection is made by the RJA_E bit (RJACF, 27H...).
Figure
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]
bits (RJACF, 27H...). Accordingly, the constant delay produced by the
Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-bit FIFO is used
when large jitter tolerance is expected, while the 32-bit FIFO is used in
delay sensitive applications.
FUNCTIONAL DESCRIPTION
IDT82P5088
CVn/RDNn
CVn/RDN1
RDn/RDPn
RDn/RDP1
TDn/TDPn
TDn/TDP1
In applications using only seven channels, channel 1 can be configured
The Receive Jitter Attenuator of each link can be chosen to be used
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
The FIFO is used as a pool to buffer the jittered input data, then the
RCLKn
RCLK1
TCLKn
TCLK1
LOSn
TDNn
LOS1
TDN1
7.
Figure-12
LOS/AIS
HDB3/AMI
LOS/AIS
HDB3/AMI
Detector
HDB3/AMI
Detector
HDB3/AMI
Decoder
Decoder
Encoder
Encoder
B8ZS/
B8ZS/
B8ZS/
B8ZS/
Loopback
Remote
illustrates the concept.
Attenuator
Attenuator
Attenuator
Attenuator
Jitter
Jitter
Jitter
Jitter
Figure-12 G.772 Monitoring Diagram
Clock and
Clock and
Recovery
Recovery
Data
Data
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Shaper/LBO
Shaper/LBO
Waveform
Waveform
26
Slicer
Slicer
Data
Data
1's Clock and Data Recovery. The signal can be observed digitally at the
RCLK1, RD1/RDP1 and RDN1. If Channel 1 is configured to Remote Loop-
back while in the Monitoring mode, the monitored data will be output on
TTIP1/TRING1.
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter whose
frequency is lower than the CF passes through the DPLL without any
attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or
1.26 Hz, as selected by the RJA_BW bit. In E1 applications, the CF of
the DPLL can be 6.77 Hz or 0.87 Hz, as selected by the RJA_BW bit
(RJACF, 27H...). The lower the CF is, the longer time is needed to
achieve synchronization.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
The monitored line signal (transmit or receive) goes through Channel
The DPLL is used to generate a de-jittered clock to clock out the data
If the incoming data moves faster than the outgoing data, the FIFO
Driver
Driver
Line
Line
Equalizer
Equalizer
Adaptive
Adaptive
Channel N (N > 2)
Channel 1
Termination
Termination
Termination
Termination
Transmitter
Transmitter
Receiver
Receiver
Internal
Internal
Internal
Internal
Monitor
G.772
February 5, 2009
TTIPn
TTIP1
RTIPn
RRINGn
TRINGn
RTIP1
RRING1
TRING1