TRC105 RFM, TRC105 Datasheet - Page 6

• Manufacturer Part Number: TRC105
• Description: IC TXRX 300MHZ-510MHZ 32TQFN
• Manufacturer: RFM

Specifications of TRC105

• Frequency: 300MHz ~ 510MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Wireless Frequency: 300 MHz to 510 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 1.7 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 583-1159-2

The transmitter chain is based on the same double-conversion architecture and uses the same intermediate fre-
quencies as the receiver chain. The main blocks include:
The frequency synthesizer is based on an integer-N PLL having an typical frequency step size of 12.5 kHz. Two
programmable frequency dividers in the feedback loop of the PLL and one programmable divider on the reference
oscillator allow the LO frequency to be adjusted. The reference frequency is generated by a crystal oscillator run-
ning at 12.8 MHz.
The TRC105 is controlled by a digital block that includes registers to store the configuration settings of the radio.
These registers are accessed by a host microcontroller through an SPI style serial interface. The microcontroller’s
serial connections to the TRC105’s SDI, SDO and SCK pins are shown in Figure 2 (component values shown are
for 418.00-434.79 MHz operation; see Tables 57 and 58 for other frequency bands). On-chip regulators provide
stable supply voltages to sensitive blocks and allow the TRC105 to be used with supply voltages from 2.1 to
3.6 V. Most blocks are supplied with a voltage below 1.6 V.
www.RFM.com
©2009-2010 by RF Monolithics, Inc.
•
•
•
•
•
A two-stage IF filter followed by an amplifier chain for both the I and Q channels. Limiters at the end of
each chain drive the I and Q inputs to the FSK demodulator function. An RSSI signal is also derived from
the I and Q IF amplifiers to drive the OOK detector. The second filter stage in each channel can be con-
figured as either a third-order Butterworth low-pass filter for FSK operation or an image reject polyphase
band-pass filter for OOK operation.
An FSK arctangent type demodulator driven from the I and Q limiter outputs, and an OOK demodulator
driven by the RSSI signal. Either detector can drive a data and clock recovery function that provides
matched filter enhancement of the demodulated data.
A digital waveform generator that provides the I and Q base-band signals. This block includes digital-to-
analog converters and anti-aliasing low-pass filters.
A compound image-rejection mixer to up convert the base-band signal to the first IF at 1/9th of the carrier
frequency, and a second image-rejection mixer to up-convert the IF signal to the RF frequency
Transmitter driver and power amplifier stages to drive the antenna port
E-mail:
[e-mail]
Technical support +1.800.704.6079
Figure 2
TRC105 - 11/01/10
Page 6 of 66
C17
1.2 pF
C16
DNP