TRC105 RFM, TRC105 Datasheet - Page 53

• Manufacturer Part Number: TRC105
• Description: IC TXRX 300MHZ-510MHZ 32TQFN
• Manufacturer: RFM

Specifications of TRC105

• Frequency: 300MHz ~ 510MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Wireless Frequency: 300 MHz to 510 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 1.7 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 583-1159-2

It is generally a good practice to set the OOK rise and fall time to about 5% of a bit period to avoid excessive
modulation bandwidth:
Where t
20/10 µs rise/fall times given in the table above are satisfactory. When operating in the 434 MHz band under ETSI
EN300 220-1 regulations, check the modulation bandwidth carefully at bit rates above 8 kb/s to confirm compli-
ance. For operation in certain parts of the 434 MHz band, the required rise and fall time may be greater than 5%.
6.4 Frequency Synthesizer Channel Programming for FSK Modulation
When using a standard 12.8 MHz reference crystal, the FSK RF channel frequency is:
Where F
registers that hold the values of P, S and R:
MCFG05 bit 0 selects the register set to use with the frequency synthesizer. A 0 value selects register set
MCFG06-MCFG08 and a 1 value selects register set MCFG09-MCFG0B. In addition, MCFG00 bits 4..2 select the
VCO operating band as follows:
The dual register set allows a new frequency to be completely entered in one register set while operating on the
other register set. It is important to load all three divider parameters into a register set before switching control to
it. Otherwise, a transient out-of-band frequency shift can occur. The dual register set facilitates FHSS operation,
as the operating frequency for the next hop can be loaded anytime during the current hop interval, making this
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OOK
t
F
RF
OOK
RF
is in MHz, and P, S, and R are divider integers with S less than (P + 1). There are two sets of three
is the nominal 5% OOK rise/fall time in µs and BR is the bit rate in kb/s. At low OOK data rates the
= 14.4*(75*(P + 1) + S)/(R + 1), with P and S in the range 0 to 255, R in the range 64 to 169
= 50/BR
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Pattern of Bits 4..3
00
01
10
11
MCFG00 bits 4..2
Regulator Rise/Fall Times
MCFG0A
MCFG0B
Register
MCFG06
MCFG07
MCFG08
MCFG09
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000
001
010
011
100
101
8.5/8.5 µs
15/15 µs
23/23 µs
3/3 µs
Table 67
Table 68
Table 69
Divider Parameter
Band, MHz
300-330
330-365
365-400
400-440
440-470
470-510
R1
P1
S1
R2
P2
S2
OOK Rise/Fall Time
20/10 µs
2.5/2 µs
10/6 µs
5/3 µs
TRC105 - 11/01/10
Page 53 of 66