AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 697

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6242E–ATARM–11-Sep09
Doc. Rev.
6242B
6242A
Comments
Updated references to USBCK (HCK0) and LCDCK (HCK1) in
Controller” on page
page
Added Note
care” NAND Flash interface.
Updated
In
access in Idle Mode.
Updated
Updated
Errata: Added
41.2.2.2 “Boot ROM: Watchdog Disable” on page 668
Range” on page
Added
page
Added
Added
behavior when CSAAT=1 and SCBR = 1” on page
Transfer) Behavior” on page
Section 41.2.7.6 “SPI: Software reset” on page
Added
Operate Correctly” on page
41.2.10.4 “TWI: Possible Receive Holding Register Corruption” on page
Software reset” on page 673
Added
41.2.11.2 “USART: RTS unexpected behavior” on page
First issue.
Table 38-3, “Power Consumption for Different Modes(1),” on page
23.
670.
Section 41.2.5.1 “NTRST: Device does not boot correctly due to power-up sequencing issue” on
Section 41.2.6.1 “SDRAM: JEDEC standard compatibility” on page
Section 41.2.7.1 “SPI: Pulse Generation on SPCK” on page
Section 41.2.10.1 “TWI: Clock Divider” on page
Section 41.2.11.1 “USART: CTS signal in Hardware Handshake” on page 674
Table 38-1, “Absolute Maximum Ratings*,” on page
Table 38-5, “Processor Clock Waveform Parameters,” on page
Section 38.5 “Crystal Oscillator Characteristics” on page
(3)
to
Section 41.2.2.1 “Boot ROM: NAND Flash Boot is not functional” on page
669.
Table 20-4, “EBI Pins and External Devices Connections,” on page 141
23. Updated
673,
671,
and
Figure 9-3, “Power Management Controller Block Diagram,” on
Section 41.2.10.3 “TWI: NACK Status Bit Lost” on page
Section 41.2.10.6 “TWI: STOP not generated” on page
Section 41.2.7.4 “SPI: Chip Select and fixed mode” on page 671
671.
671,
and
672,
Section 41.2.7.3 “SPI: LASTXFER (Last
674.
Section 41.2.2.3 “Boot ROM: Temperature
Section 41.2.10.2 “TWI: Disabling Does not
655.
Section 9.6 “Power Management
659.
670,
657, added Note
Section 41.2.7.2 “SPI: Bad PDC
673,
658.
670.
Section 41.2.10.5 “TWI:
AT91SAM9261S
and
(1)
668,
for CE “Don’t
673.
on SRAM
673,
Section
Section
Section
and
Change
Request
Ref.
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