AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 672

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

42.2.8
42.2.8.1
42.2.8.2
42.2.8.3
42.2.9
42.2.9.1
42.2.9.2
672
AT91SAM9261S
SDRAM Controller
Serial Peripheral Interface (SPI)
SDRAM: SDCLK Clock Active After Reset
SDRAM: JEDEC Standard Compatibility
SDRAM: Mobile SDRAM Device Initialization Constraint
SPI: Pulse Generation on SPCK
SPI: Bad PDC Behavior when CSAAT=1 and SCBR = 1
After a reset the SDRAM clock is always active leading in over consumption in the pad.
The following sequence allows to stop the SDRAM clock.
In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be stable before the rising
edge of SDCKE. This is not the case in this product.
Use a fully JEDEC compliant SDRAM module.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile
SDRAM device initialization, may lead to data bus contention. Therefore, external memories on
the same EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
Do not use this configuration.
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
None. Do not use the combination CSAAT=1 and SCBR =1.
1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
complete.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0.
6242E–ATARM–11-Sep09