AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 693

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6242E–ATARM–11-Sep09
Doc. Rev.
6242C
Date
12-Sep-08 Comments
Ordering Information:
Section 41. ”AT91SAM9261S Ordering Information”
Updated with Revision B Parts: AT91SAM9261SB-CU
Errata:
Section 42.3 ”AT91SAM9261S Errata - Revision B Parts”
removed errata USART “CTS signal in Hardware Handshake...” from Revision A Errata
Section 42.2.7.1 on page
New!!!
Address Offsets added to register tables in User Interface sections of the datasheet.
Section 7.2 ”Debug and Test
AIC:
Section 27.8.15 ”AIC Spurious Interrupt Vector
Section 27.6.3 ”Interrupt
Section 27.7.5 ”Protect
ARM926EJ-S Processor
Section 11.1
Removed the block diagram.
Debug and Test:
Table 12-2, “AT91SAM9261S JTAG Boundary Scan Register”
Name A19.
GPBR:
Section 19. ”General Purpose Backup Register
LCDC:
Table 38-1, “I/O Lines
Section 38.5.1.3
mode. Updated definitions.
Table 38-4, “Big Endian Memory
Section 38.10.23 ”Power Control
“pin” to “signal”.
Section 38.10.1 ”DMA Base Address Register
Section 38.5.2.7
Section 38.9.2 ”TFT Mode
”Overview”, removed last bullet on TCM interface.
”Channel-U”, Removed equations for STN Monochrome mode and STN Color
”Shifter”, fixed typo: “LDCCON3 register” corrected to read “LCDCON2 register”
Description”, updated description of LCDDEN.
Mode”, enabling Debug Control Protect Mode in AIC_DCR register updated. 5193
Sources”, Interrupt Source 1 OR-wiring description updated.
671, effect on ETM9 removed from NTRST errata.
Example”, HFP = (16-2), HBP = (48 -1), HPW = (64-1), typo corrected.
Features”, removed ETM9 list.
Organization”, Inverted Pixel 1bpp row values to go from 0 to 31.
Register”, LCD_PWR bit description, changed all occurrences of
1”, updated with new values for bits 0 and 1.
Register”, fixed typo in bitfields.
(GPBR)”, added to the datasheet
has been added
Bit number 481 is assigned to Pin
AT91SAM9261S
Change
Request
Ref.
5487
5433
5186
5794
rfo
5794
4749
5191
5794
5530
5764
3587
4268
4488
4739
5619
693