AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 589

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

38.3
Table 38-1.
38.4
38.4.1
38.4.2
38.4.3
38.5
38.5.1
38.5.1.1
38.5.1.2
6242E–ATARM–11-Sep09
Name
LCDCC
LCDHSYNC
LCDDOTCK
LCDVSYNC
LCDDEN
LCDD[23:0]
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Power Management
Interrupt Sources
DMA Controller
Configuration Block
AHB Interface
I/O Lines Description
Description
Contrast control signal
Line synchronous signal (STN) or Horizontal synchronous signal (TFT)
LCD clock signal (STN/TFT)
Frame synchronous signal (STN) or Vertical synchronization signal (TFT)
Data enable signal
LCD Data Bus output
The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The pro-
grammer must first program the PIO Controller to assign the pins to their peripheral function. If
I/O lines of the LCD Controller are not used by the application, they can be used for other pur-
poses by the PIO Controller.
The LCD Controller is not continuously clocked. As the LCD Controller is on the AHB bus, the
clock is enabled by setting the HCKx bit in the PMC_SCER register.
The LCD Controller interrupt line is connected to one of the internal sources of the Advanced
Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC.
The LCD Controller consists of two main blocks
and the LCD controller core (LCDC core). The DMA controller reads the display data from an
external memory through a AHB master interface. The LCD controller core formats the display
data. The LCD controller core continuously pumps the pixel data into the LCD module via the
LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK, LCDDEN, LCDHSYNC, and
LCDVSYNC signals.
The configuration block is a set of programmable registers that are used to configure the DMA
controller operation. These registers are written via the AHB slave interface. Only word access is
allowed.
For details on the configuration registers, see
613.
This block generates the AHB transactions. It generates undefined-length incrementing bursts
as well as 4- ,8- or 16-beat incrementing bursts. The size of the transfer can be configured in the
“LCD Controller (LCDC) User Interface” on page
(Figure 38-1 on page
AT91SAM9261S
588), the DMA controller
Output
Output
Output
Type
Output
Output
Output
589