AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 695

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6242E–ATARM–11-Sep09
Doc. Rev.
6242C
Date
12-Sep-08 Comments (Continued)
TC:
Section 34.6 ”Timer Counter (TC) User
Table 34-4, “Register Mapping”
From
register names updated with indexed offset reference. Functional value of WAVE is given, when
relevant, in Register Name or Access.
Section 34.6.2 ”TC Block Mode
Section 34.6.4 ”TC Channel Mode Register: Capture
Section 34.6.5 ”TC Channel Mode Register: Waveform
TWI:
Section 31. ”Two Wire Interface
UDP:
Table 37-2, “USB Communication Flow”
“Supported Endpoint Size” column.
Control endpoints are not effected by the
UDP_CSR register.
Updated “write 1 =....” in
Updated “write 0 =....” in
Section 37.6.10 ”UDP Endpoint Control and Status
regarding USB clock and system clock cycle.
by Master Clock domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral
clock requirements.
Table 37-4, “Register
footnote added to UDP_ISR reset.
Section 37.6.6 ”UDP Interrupt Mask
Table 37-4, “Register
Table 37-1, “USB Endpoint
Section 37.5.2.9 ”Transmit Data
Section 37.6.9 ”UDP Reset Endpoint
”TXPKTRDY: Transmit Packet
UHP:
Section 36.1
http://h18000.www1.hp.com/productinfo/development/openhci.html.
USART:
Section 32.5.1 ”I/O
hardware handshaking feature.
Section 32.6.2 ”Receiver and Transmitter
(RSTRX and RSTTX in US_CR register) updated by replacing 2nd sentence.
Section 32.6.3.1 ”Transmitter
Section 32.6.5 ”IrDA
Section 37.2 ”Block
Section 34.6.3 ”TC Channel Control Register”
”Overview”, Added hyperlink to Open HCI Rev 1.0 Specification.
Lines”, added sentence on required use of internal pull up on TXD pertaining to
Diagram”, text under the block diagram updated: MCK specified as clock used
Mode”, updated with instructions to receive IrDA signals.
Mapping”, UDP_CSR, UDP_FDR updated with indexed register scheme,
Mapping”, Reset value for UDP_RST_EP is 0x000_0000
”RX_DATA_BK0: Receive Data Bank 0”
”TXPKTRDY: Transmit Packet Ready”
Description”, footnote added to Dual-Bank heading.
Operations”, last paragraph updated.
Ready”, description in UDP_CSRx, updated “Write :0 = .....“.
as a result of indexed register scheme.
Register”, typo corrected in bit fields 2 and 3.
(TWI)”, extensive update to this section.
Cancellation”, added.
Register”, bitfield 12 defined as BIT12, cannot be masked.
Register”, added steps to clear endpoints.
Interface”, previous Register Mapping tables consolidated in
changed the value in the cell on the “interrupt line of the
”EPEDS: Endpoint Enable Disable”
Control”, In the fourth paragraph, Software reset effects
Register”, update to code and added instructions
to
Mode”, bit field 15 updated.
Section 34.6.13 ”TC Interrupt Mask
Mode”, bit field 15 updated.
bit field of UDP_CSR register.
bit field of UDP_CSR register.
bit field in the
AT91SAM9261S
Register”,
Change
Request
Ref.
4583
5327
3476
4063
4099
4462/4487
4508
4802
5049
5150
4364
4285
4367
rfo
4912
695