AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 683

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

42.3.6.4
42.3.6.5
42.3.7
42.3.7.1
42.3.8
42.3.8.1
42.3.8.2
42.3.8.3
6242E–ATARM–11-Sep09
NTRST
SDRAM Controller
MCI: Data Write Operation and Number of Bytes
NTRST: Device Does Not Boot Correctly Due To Power-up Sequencing Issue
SDRAM: JEDEC Standard Compatibility
MCI: STOP During a WRITE_MULTIPLE_BLOCK Command
SDRAM: SDCLK Clock Active After Reset
SDRAM: Mobile SDRAM Device Initialization Constraint
The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is
not stopped by the STOP command.
Choose an appropriate size for the block length.
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is pow-
ered by VDDCORE power supply (1.2V).
During the power-up sequence, if VDDIOP power supply is not established whereas the
VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. The
ARM processor then enters debug state and the device does not boot correctly.
After a reset the SDRAM clock is always active leading in over consumption in the pad.
The following sequence allows to stop the SDRAM clock.
In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be stable before the rising
edge of SDCKE. This is not the case in this product.
Use a fully JEDEC compliant SDRAM module.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile
SDRAM device initialization, may lead to data bus contention. Therefore, external memories on
the same EBI must not be accessed.
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes
2. Connect NTRST to GND if no debug capabilities are required.
1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
place in all cases.
complete.
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