AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 44

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.2.9
11.2.10
44
AT91SAM9261S
New ARM Instruction Set
Thumb Instruction Set Overview
Table 11-2.
Table 11-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Mnemonic
Mnemonic
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMLAWy
SMULWy
LDRBT
SMULxy
SMLAxy
QDADD
QDSUB
SMLAL
LDRT
BLX
QADD
SWP
MCR
QSUB
LDM
CDP
LDC
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
ARM Instruction Mnemonic List (Continued)
New ARM Instruction Mnemonic List
Operation
Load Register Byte with
Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data Processing
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16
* 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate 32
* 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Mnemonic
Mnemonic
STRBT
SWPB
MRRC
MCRR
STRT
MCR2
STRD
LDRD
CDP2
BKPT
STC2
LDC2
STM
MRC
STC
PLD
CLZ
Operation
Store Register Byte with
Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare
to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Coprocessor
Count Leading Zeroes
Alternative Load to
6242E–ATARM–11-Sep09