AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 670

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

42.2.5.2
42.2.5.3
670
AT91SAM9261S
LCD: Periodic Bad Pixels
LCD: 24-bit Packed Mode
Powering LCD off, then powering LCD on, resets the FIFO pointers.
Disabling DMA, then enabling DMA, resets the DMA pointers.
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per-
forms bursts to read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA
boundary.
The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG
register.
The LCD DMA Base Address is programmed in DMABADDR1 register.
The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst
size, e.g.:
BRSTLN = 15
For a 16-word burst, the LCD DMA Base Address must start on a 16-word offset: 0x0, 0x40,
0x80 or 0xc0.
BRSTLN = 3
For a 4-word burst, the LCD DMA Base Address offset must start on a 4-word offset: 0x0, 0x10,
..., 0xf0.
LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed
mode. A 32-bit word contains some bits of a pixel and some bits of the following. If LCD DMA
Base Address is not aligned with a pixel start, the colors will be modified.
Respect "LCD periodic bad pixels" erratum constrains lead to select the LCD DMA Base
Address regarding the LCD DMA burst size.
Problem Fix/Workaround
LCD DMA Base Address is to be set on a pixel start, every three 32-bit word.
The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or
0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8,
0xb4, 0xc0 ...)
e.g. regarding the bursts size:
1) BRSTLN = 3 implies the following LCD DMA Base Address offsets: 0x0, 0x30, 0x60, ...
2) BRSTLN = 15 implies the following LCD DMA Base Address offsets: 0x0 and 0xc0 only.
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
Problem Fix/Workaround
6242E–ATARM–11-Sep09