AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet
AT91SAM9261SB-CU-999
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AT91SAM9261SB-CU-999 Summary of contents
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Features • Incorporates the ARM926EJ-S™ ARM – DSP Instruction Extensions ® – ARM Jazelle Technology for Java – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit ™ – ...
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... Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel EEPROMs Supported ® • IEEE 1149.1 JTAG Boundary Scan on All Digital Pins • ...
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Description The AT91SAM9261S is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261S is an optimized host processor for ...
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Block Diagram Figure 2-1. AT91SAM9261S Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG ...
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Signal Description Table 3-1. Signal Description by Peripheral Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDPLL PLL Power Supply VDDOSC Oscillator Power Supply VDDCORE Core ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - PA31 Parallel IO Controller A PB0 - PB31 Parallel IO Controller B PC0 - PC31 Parallel IO Controller ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function SCK0 - SCK2 Serial Clock TXD0 - TXD2 Transmit Data RXD0 - RXD2 Receive Data RTS0 - RTS2 Request To Send CTS0 - CTS2 Clear To Send TD0 - TD2 ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function HDMA USB Host Port A Data - HDPA USB Host Port A Data + HDMB USB Host Port B Data - HDPB USB Host Port B Data + AT91SAM9261S 8 ...
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Package and Pinout The AT91SAM9261S is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9261S Mechanical ...
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Pinout Table 4-1. AT91SAM9261S Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC ...
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Power Considerations 5.1 Power Supplies The AT91SAM9261S has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: ...
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Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma- nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this ...
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Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
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Debug and Test Features • Integrated Embedded In-circuit Emulator Real-Time – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • ...
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Memories Figure 8-1. AT91SAM9261S Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF ...
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space ...
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Internal Memory Mapping Table 8-3 status and the BMS state at reset. Table 8-3. Internal Memory Mapping Address Master 0: ARM926 Instruction REMAP(RCB0 BMS = 1 0x0000 0000 Int. ROM Note: 1. EBI NCS0 ...
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BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. • Enable the 32,768 Hz oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Automatic ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF ...
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Block Diagram Figure 9-1. System Controller Block Diagram periph_irq[2..21] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset VDDCORE Powered NRST VDDCORE POR VDDBU POR backup_nreset SHDN WKUP backup_nreset VDDBU Powered XIN32 SLOW CLOCK XOUT32 OSC XIN MAIN ...
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Reset Controller • Based on two Power-on-Reset cells • Status of the last reset – Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset • Controls the internal resets and the NRST pin output 9.3 ...
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Power Management Controller • The Power Management Controller provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clock USBCK (HCK0) – the LCD Controller Clock LCDCK (HCK1) – thirty peripheral clocks – ...
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... Chip ID Registers – ICE Access Prevention • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...
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Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of • ICE Access prevention – Enables software to prevent system access ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory ...
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Peripheral Multiplexing on PIO Lines The AT91SAM9261S features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one ...
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SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard useful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI. 10.3.1.7 USARTs • Using USART0 with its ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A Peripheral B PA0 SPI0_MISO MCDA0 PA1 SPI0_MOSI MCCDA PA2 SPI0_SPCK MCCK PA3 SPI0_NPCS0 PA4 SPI0_NPCS1 MCDA1 PA5 SPI0_NPCS2 MCDA2 PA6 SPI0_NPCS3 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 LCDVSYNC PB1 LCDHSYNC PB2 LCDDOTCK PCK0 (1) PB3 LCDDEN PB4 LCDCC LCDD2 PB5 LCDD0 LCDD3 PB6 LCDD1 LCDD4 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Peripheral B PC0 NANDOE NCS6 PC1 NANDWE NCS7 PC2 NWAIT IRQ0 PC3 A25/CFRNW PC4 NCS4/CFCS0 PC5 NCS5/CFCS1 PC6 CFCE1 PC7 CFCE2 ...
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System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • ...
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Static Memory Controller • External memory mapping, 256 Mbyte address space per Chip Select Line • Eight Chip Select Lines • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte ...
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Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, ...
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Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, ...
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USB • USB Host Port: – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with ...
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AT91SAM9261S 36 6242E–ATARM–11-Sep09 ...
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ARM926EJ-S Processor Description 11.1 Overview The ARM926EJ-S processor is a member of the ARM9 sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and ...
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ARM9EJ-S Processor 11.2.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable ...
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Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. ...
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Table 11-1. User and System Mode R11 R12 R13 R14 PC CPSR The ARM state register set contains 16 directly-accessible registers r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose ...
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CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 11.2.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five ...
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When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep- tions according ...
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If the instruction is not executed, for example because a branch occurs while the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve ...
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Table 11-2. Mnemonic LDRBT LDRT LDM SWP MCR LDC CDP 11.2.9 New ARM Instruction Set Table 11-3. Mnemonic BXJ BLX SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 11.2.10 Thumb Instruction Set Overview The Thumb instruction set is ...
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Table 11-4 Table 11-4. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC 6242E–ATARM–11-Sep09 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare ...
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CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • MMU • Other system options To control ...
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CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) ...
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Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian OS Linux. These virtual memory features are memory access permission controls and virtual ...
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Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic ...
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Caches and Write Buffer The ARM926EJ-S contains Instruction Cache (ICache Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches ...
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DCache can be enabled or disabled by writing either 1 ...
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... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. ...
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AT91SAM9261S Debug and Test 12.1 Overview The AT91SAM9261S features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 on page 54 face is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debug- ger ...
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Test Environment Figure 12-3 on page 55 preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure ...
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... JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149. Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2 ...
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Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with ...
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Table 12-2. Bit Number 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 AT91SAM9261S 58 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 439 438 D5 437 436 435 D6 434 433 432 D7 431 430 429 D8 428 427 426 425 D9 424 423 422 D10 421 420 419 ...
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Table 12-2. Bit Number 404 403 402 401 400 399 398 397 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 368 367 PC23 366 365 364 363 PC24 362 361 360 359 PC25 358 357 356 355 PC26 354 353 352 351 PC27 350 349 348 347 ...
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Table 12-2. Bit Number 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 296 295 PC11 294 293 292 291 PC12 290 289 288 287 PC13 286 285 284 283 PC14 282 281 280 279 PC15 278 277 276 275 ...
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Table 12-2. Bit Number 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 224 223 PA13 222 221 220 219 PA14 218 217 216 215 PA15 214 213 212 211 PA16 210 209 208 207 PA17 206 205 204 203 ...
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Table 12-2. Bit Number 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 152 151 PA31 150 149 148 147 PB0 146 145 144 143 PB1 142 141 140 139 PB2 138 137 136 135 PB3 134 133 132 131 ...
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Table 12-2. Bit Number 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AT91SAM9261S 68 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name PB8 PB9 PB10 PB11 99 PB12 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 80 79 PB17 PB18 PB19 PB20 PB21 ...
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Table 12-2. Bit Number AT91SAM9261S 70 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 44 43 PB26 PB27 PB28 PB29 PB30 ...
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Table 12-2. Bit Number 6242E–ATARM–11-Sep09 AT91SAM9261S JTAG Boundary Scan Register (Continued) Pin Name 08 A10 07 SDA10 06 A11 05 A12 04 A13 03 A14 02 A15 01 A16 00 A17 AT91SAM9261S Pin Type Associated BSR Cells OUT OUTPUT OUT ...
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ID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B08 • MANUFACTURER IDENTITY[11:1] Set ...
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AT91SAM9261S Boot Program 13.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. ...
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Flow Diagram The Boot Program implements the algorithm in Figure 13-1. Boot Program Algorithm Flow Diagram SPI Serial Flash Boot No SPI DataFlash Boot No Nand Flash Boot AT91SAM9261S 74 Device Setup Yes Download from Serial ...
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Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. Main Oscillator Frequency Detection 3. C variable initialization 4. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use ...
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Figure 13-2. Remap Action after Download Completion 13.4 Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corre- sponding to the ARM exception vectors. These bytes must implement ARM instructions for ...
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Figure 13-5. Structure of the ARM Vector 6 31 13.4.2.1 Example An example of valid vectors follows The size of the image to load into SRAM is contained in the location of the ...
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Figure 13-6. Serial Flash Download 13.6 DataFlash Boot Sequence The Dataflash boot looks for a valid application in the SPI DataFlash memory. SPI0 is configured in master mode to generate a SPCK at 8MHz. Serial Flash shall be con- nected ...
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If the dataflash is ready, DataFlash boot reads the first 8 words into SRAM (Instruction code “Continuous Read Array” 0x0b) and checks if it corresponds to valid exception vectors according to the Valid Image detection algorithm valid application ...
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NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after ...
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Table 13-2. Command • Write commands: Write a byte (O), a halfword ( word (W) to the target. – Address: Address in hexadecimal. – Value: Byte, halfword or ...
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... ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. ...
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... Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 13.10.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration send- ing requests to the device through the control endpoint ...
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Hardware and Software Constraints • The DataFlash, SerialFlash, NAND Flash, SDCard must be inferior to 12 Kbytes. • The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • ...
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Table 13-5. Peripheral TWI DBGU DBGU 6242E–ATARM–11-Sep09 Pins Driven during Boot Program Execution Pin TWD DRXD DTXD AT91SAM9261S PIO Line PIOA7 PIOA9 PIOA10 85 ...
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AT91SAM9261S 86 6242E–ATARM–11-Sep09 ...
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Reset Controller (RSTC) 14.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
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Functional Description 14.3.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset ...
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The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when ...
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Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed ...
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Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is ...
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When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the ...
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The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. If EXTRST is set, ...
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If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after ...
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Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed ...
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Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9261S 96 read RSTC_SR 2 cycle resynchronization 6242E–ATARM–11-Sep09 ...
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Reset Controller (RSTC) User Interface Table 14-1. Register Mapping Offset Register 0x00 Control Register (1) 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on ...
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Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFD00 Access Type:Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets ...
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Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFD04 Access Type:Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFD08 Access Type:Read-write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the ...
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Real-time Timer (RTT) 15.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 15.2 Block Diagram Figure 15-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6242E–ATARM–11-Sep09 AT91SAM9261S Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 ...
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Real-time Timer Mode Register Name: RTT_MR Address: 0xFFFFFD20 Access Type: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the ...
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Real-time Timer Alarm Register Name: RTT_AR Address: 0xFFFFFD24 Access Type: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register Name: ...
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Real-time Timer Status Register Name: RTT_SR Address: 0xFFFFFD2C Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not ...
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Periodic Interval Timer (PIT) 16.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 Block Diagram Figure 16-1. ...
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Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging ...
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Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register 6242E–ATARM–11-Sep09 AT91SAM9261S Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR ...
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Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFD30 Access Type: Read/Write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of ...
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Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFD34 Access Type: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic Interval ...
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Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFD38 Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of ...
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Watchdog Timer (WDT) 17.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9261S 115 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6242E–ATARM–11-Sep09 ...
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Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9261S 116 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6242E–ATARM–11-Sep09 ...
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Watchdog Timer Control Register Register Name:WDT_CR Address: 0xFFFFFD40 Access Type: Write-only – – – – – – • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password ...
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Watchdog Timer Mode Register Register Name: WDT_MR Address: 0xFFFFFD44 Access Type: Read-write Once 31 30 WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...
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Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9261S 119 6242E–ATARM–11-Sep09 ...
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Watchdog Timer Status Register Register Name: WDT_SR Address: 0xFFFFFD48 Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the ...
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Shutdown Controller (SHDWC) 18.1 Overview The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.2 Block Diagram Figure 18-1. Shutdown Controller Block Diagram Shutdown Controller SHDW_MR CPTWK0 WKMODE0 WKUP0 RTTWKEN ...
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A typical application connects the pin viding the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system. The software is able to control ...
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Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 18.6.1 Shutdown Control Register Register Name: SHDW_CR Address: 0xFFFFFD10 Access Type: Write-only ...
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Shutdown Mode Register Register Name: SHDW_MR Address: 0xFFFFFD14 Access Type: Read/Write 31 30 – – – – – CPTWK0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None. No ...
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Shutdown Status Register Register Name: SHDW_SR Address: 0xFFFFFD18 Access Type: Read-only 31 30 – – – – – – – – • WAKEUP0: Wake-up 0 Status wake-up event occurred on ...
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AT91SAM9261S 126 6242E–ATARM–11-Sep09 ...
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General Purpose Backup Register (GPBR) 19.1 Overview The System Controller embeds 4 general-purpose backup registers. 19.2 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xC General ...
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General Purpose Backup Register x Register Name:SYS_GPBRx Addresses: 0xFFFFFD50 [0], 0xFFFFFD54 [1], 0xFFFFFD58 [2], 0xFFFFFD5C [3] Access Type: Read-write • GPBR_VALUEx: Value of GPBR x AT91SAM9261S 128 GPBR_VALUEx ...
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AT91SAM9261S Bus Matrix 20.1 Overview The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects ...
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Arbitration The Bus Matrix provides an arbitration function that reduces latency when conflicting cases occur, i.e., when two or more masters try to access the same slave at the same time. The Bus Matrix arbitration mechanism uses slightly modified ...
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Bus Matrix (MATRIX) User Interface Table 20-1. Register Mapping Offset Register 0x0000 Master Configuration Register 0x0004 Slave Configuration Register 0 0x0008 Slave Configuration Register 1 0x000C Slave Configuration Register 2 0x0010 Slave Configuration Register 3 0x0014 Slave Configuration Register ...
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Bus Matrix Master Configuration Register Name: MATRIX_MCFG Address: 0xFFFFEE00 Access Type:Write only 31 30 – – – – – – – – • RCBx: Remap Command Bit for AHB Master ...
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Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...MATRIX_SCFG4 Address: 0xFFFFEE04 Access Type:Read-write 31 30 – – – – – • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is ...
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EBI Chip Select Assignment Register Name: EBI_CSA Address: 0xFFFFEE30 Access Type:Read-write Reset: 0x0000_0000 31 30 – – – – – – – – EBI_CS5A • EBI_CS1A: EBI Chip Select 1 Assignment 0 = ...
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USB Pad Pull-up Control Register Name: USB_PUCR Address: 0xFFFFEE34 Access Type:Read-write Reset: 0x0000_0000 31 30 Reserved UDP_PUP_ON 23 22 – – – – – – • UDP_PUP_ON: UDP Pad Pull-up Enable 0: Pad pull-up disabled ...
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AT91SAM9261S 136 6242E–ATARM–11-Sep09 ...
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External Bus Interface (EBI) 21.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory and SDRAM Controllers are ...
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Block Diagram Figure 21-1 Figure 21-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9261S 138 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Logic Static Memory Controller NAND Flash ...
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I/O Lines Description Table 21-1. I/O Lines Description Name Function D0 - D31 Data Bus A0 - A25 Address Bus NWAIT External Wait Signal NCS0 - NCS7 Chip Select Lines NWR0 - NWR3 Write Signals NRD Read Signal NWE ...
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The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 21-2 on page 140 EBI pins. Table 21-2. NWR1/NBS1/CFIOR A0/NBS0 A1/NBS2/NWR2 A[11:2] SDA10 A12 A[14:13] A[25:15] ...
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Table 21-3. EBI Pins and External Static Devices Connections (Continued) 8-bit Static Device Pins Controller NCS5/CFCS1 CS NCS6/NAND0E CS NCS7/NANDWE CS NRD/CFOE OE NWR0/NWE WE NWR1/NBS1 – NWR3/NBS3 – Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte ...
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Table 21-4. EBI Pins and External Devices Connections (Continued) Pins Controller A23 - A24 A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NCS6/NANDOE NCS7/NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 CFCE2 SDCK SDCKE RAS CAS SDWE NWAIT (2) Pxx (2) Pxx (2) ...
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Connection Examples Figure 21-2 Figure 21-2. EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD NWR0/NWE SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 21.5 Product ...
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Functional Description The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter- nal memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control busses ...
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I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. ...
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The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 21-6. CFCE1 and CFCE2 Truth Table Mode CFCE2 Attribute Memory NBS1 NBS1 Common ...
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Figure 21-4. CompactFlash Read/Write Control Signals Table 21-7. CompactFlash Mode Selection Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode 21.6.5.4 Multiplexing of CompactFlash Signals on EBI Pins Table 21-8 on page 147 Flash logic signals with ...
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Table 21-9. Shared CompactFlash Interface Multiplexing Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW 21.6.5.5 Application Example Figure 21-5 on page 149 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output ...
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Figure 21-5. CompactFlash Application Example 21.6.6 NAND Flash Support The EBI integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the CS3A field in ...
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Figure 21-6. NAND Flash Signal Multiplexing on EBI Pins SMC NCS6 NCS7 NCS3 NRD NWR0_NWE The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI ...
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Figure 21-7. NAND Flash Application Example Note: 6242E–ATARM–11-Sep09 D[7:0] A[22:21] NCS3/NANDCS EBI NCS6/NANDOE NCS7/NANDWE PIO PIO The External Bus Interface is also able to support 16-bits devices. AT91SAM9261S AD[7:0] ALE CLE Not Connected NAND Flash NOE NWE CE R/B 151 ...
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Implementation Examples All the hardware configurations are given for illustration only. The user should refer to the mem- ory manufacturer web site to check the device availability. 21.7.1 16-bit SDRAM 21.7.1.1 Hardware Configuration D[0..15] A[0..14] (Not used A12) 21.7.1.2 ...
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SDRAM 21.7.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12 A10 A11 SDA10 SDA10 A13 BA0 BA0 BA1 BA1 A14 SDCKE SDCKE SDCK SDCK 1%6 A0 1%6 CFIOR_NBS1_NWR1 CAS CAS RAS ...
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NAND Flash 21.7.3.1 Hardware Configuration D[0..7] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.3.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A ...
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NAND Flash 21.7.4.1 Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode ...
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NOR Flash on NCS0 21.7.5.1 Hardware Configuration 21.7.5.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For ...
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Compact Flash 21.7.6.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 ...
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Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
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Compact Flash True IDE 21.7.7.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 A9 A8 ...
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Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
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Static Memory Controller (SMC) 22.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit ...
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Application Example 22.4.1 Hardware Interface Figure 22-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A25 Static Memory Controller 22.5 Product Dependencies 22.5.1 I/O Lines ...
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External Memory Mapping The SMC provides address lines, A[25:0]. This allows each chip select line to address Mbytes of memory. If the physical memory device connected on one chip select is smaller than ...
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Figure 22-3. Figure 22-4. Figure 22-5. Memory Connection for a 32-bit Data Bus AT91SAM9261S 164 Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] A1 ...
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Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. • For 16-bit devices: ...
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Figure 22-6. 22.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. shows signal multiplexing depending ...
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Figure 22-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) Table 22-3. SMC Multiplexed Signal Translation Signal Name Device Type 1x32-bit Byte Access Type (BAT) Byte Select NBS0_A0 NBS0 NWE_NWR0 NWE NBS1_NWR1 NBS1 NBS2_NWR2_A1 NBS2 ...
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Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE sig- nal ...
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NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: ...
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Figure 22-9. No Setup, No Hold On NRD and NCS Read Signals NBS0,NBS1, NBS2,NBS3, A0, A1 22.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. ...
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Figure 22-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD NBS0,NBS1, NBS2,NBS3, A0, A1 22.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 22-11 the falling edge of the NCS signal and remains ...
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Write Waveforms The write protocol is similar to the read protocol depicted in starts with the address setting on the memory address bus. 22.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse ...
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Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle ...
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Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi- cates which signal controls the write operation. 22.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1): Figure 22-14 put on the bus during the ...
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Figure 22-15. WRITE_MODE = 0. The write operation is controlled by NCS NBS0, NBS1, NBS2, NBS3, A0, A1 NWR0, NWR1, NWR2, NWR3 22.8.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in ...
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Reset Values of Timing Parameters Table 22-5 Table 22-5. Register SMC_SETUP SMC_PULSE SMC_CYCLE WRITE_MODE READ_MODE 22.8.7 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger ...
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Figure 22-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 D[31:0] 22.9.2 Early Read Wait State In some cases, the SMC ...
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Figure 22-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD D[31:0] Figure 22-18. Early Read Wait State: NCS Controlled Write with No Hold Followed ...
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Figure 22-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) D[31:0] 22.9.3 Reload User Configuration ...
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The instructions used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another CS. 22.9.3.2 Slow Clock Mode Transition A Reload Configuration Wait State ...
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Data Float Wait States Some memory devices are slow to release the external bus. For such devices necessary to add wait states (data float wait states) after a read access: • before starting a read access to ...
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Figure 22-20. TDF Period in NRD Controlled Read Access (TDF = 2) Figure 22-21. TDF Period in NCS Controlled Read Operation (TDF = 3) AT91SAM9261S 182 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS tpacc D[31:0] NRD controlled ...
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TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait ...
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Figure 22-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK 25:2] A[ NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read2 controlling signal (NRD) D[31:0] read1 cycle ...
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Figure 22-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] TDF_CYCLES = 5 22.11 ...
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Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchroniza- tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the ...
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Figure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6242E–ATARM–11-Sep09 FROZEN STATE ...
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Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, ...
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Figure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6242E–ATARM–11-Sep09 Read cycle EXNW_MODE = ...
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NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must ...
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Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow ...
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Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode ...
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Figure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK ...
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Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field ...
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The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page ...
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Figure 22-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6242E–ATARM–11-Sep09 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9261S NRD_PULSE 196 ...
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Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in gram the parameters of the external device connected on it bytes (0x10) are required per chip select. The user must complete writing ...
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SMC Setup Register Register Name:SMC_SETUP[0..7] Addresses: 0xFFFFEC00 [0], 0xFFFFEC10 [1], 0xFFFFEC20 [2], 0xFFFFEC30 [3], 0xFFFFEC40 [4], 0xFFFFEC50 [5], 0xFFFFEC60 [6], 0xFFFFEC70 [7] Access Type:Read-write 31 30 – – – – – – – ...
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SMC Pulse Register Register Name:SMC_PULSE[0..7] Addresses: 0xFFFFEC04 [0], 0xFFFFEC14 [1], 0xFFFFEC24 [2], 0xFFFFEC34 [3], 0xFFFFEC44 [4], 0xFFFFEC54 [5], 0xFFFFEC64 [6], 0xFFFFEC74 [7] Access Type:Read-write 31 30 – – – – • NWE_PULSE: NWE ...
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SMC Cycle Register Register Name:SMC_CYCLE[0..7] Addresses: 0xFFFFEC08 [0], 0xFFFFEC18 [1], 0xFFFFEC28 [2], 0xFFFFEC38 [3], 0xFFFFEC48 [4], 0xFFFFEC58 [5], 0xFFFFEC68 [6], 0xFFFFEC78 [7] Access Type:Read-write 31 30 – – – – • NWE_CYCLE: Total ...