AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 26

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
26
Peripheral Multiplexing on PIO Lines
AT91SAM9261S
Resource Multiplexing
LCD Controller
EBI
32-bit Data Bus
NAND Flash Interface
Compact Flash Interface
The AT91SAM9261S features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the
I/O lines of the peripheral set.
Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two
peripheral functions, A or B.
page 30
lers. The two columns “Function” and “Comments” have been inserted for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some output only peripheral functions might be duplicated within the tables.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device
is maintained in a static state as soon as the reset is released. As a result, the bit corresponding
to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel
without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the
chip select line 0 of the SPI1.
16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output
on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on
LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and
the SPI1 lines.
If not required, the NWAIT function (external wait request) can be deactivated by software,
allowing this pin to be used as a PIO.
Using a 32-bit Data Bus prevents:
Using the NAND Flash interface prevents:
Using the CompactFlash interface prevents:
• using the three Timer Counter channels’ outputs and trigger inputs
• using the SSC2
• using NCS3, NCS6 and NCS7 to access other parallel devices
• using NCS4 and/or NCS5 to access other parallel devices
define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control-
Table 10-2 on page
28,
Table 10-3 on page 29
6242E–ATARM–11-Sep09
and
Table 10-4 on