AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 681
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT91SAM9261SB-CU-999
Manufacturer Part Number
AT91SAM9261SB-CU-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261SB-CU-999.pdf
(709 pages)
Specifications of AT91SAM9261SB-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, I2S, SPI, USB
Maximum Clock Frequency
190 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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42.3.3
42.3.3.1
42.3.4
42.3.4.1
42.3.5
42.3.5.1
42.3.5.2
6242E–ATARM–11-Sep09
Boot ROM
Bus Matrix
LCD
Boot ROM: Temperature Range
Bus Matrix: Problem with Locked Transfers
LCD: Screen shifting after a reset
LCD: Periodic bad pixels
The temperature range for the Boot ROM use is 0°C / 70°C.
Starting up the device outside this temperature range can lead to unpredictable behavior. If the
AT91SAM9261S-based system may have to start up at temperatures below 0⋅ C and above
70⋅ C, it is recommended to boot out of an external memory connected on NCS0.
None.
Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freeze
up. This does not concern ARM locked transfers.
Avoid other Bus Matrix masters locked transfers.
When a FIFO underflow occurs, a reset of the LCD DMA and FIFO pointers is necessary.
If only LCD DMA pointers are reset (FIFO pointers not reset), the displayed image is shifted.
Apply the following sequence to correctly reset LCD DMA and FIFO pointers:
Powering LCD off, then powering LCD on, resets the FIFO pointers.
Disabling DMA, then enabling DMA, resets the DMA pointers.
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per-
forms bursts to read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA
boundary.
The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG
register.
The LCD DMA Base Address is programmed in DMABADDR1 register.
The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst
size, e.g.:
• LCD power off
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9261S
681
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