AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 520

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

35.7.1
6242E–ATARM–11-Sep09
Command - Response Operation
in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock
MCI Clock.
Two types of data transfer commands are defined:
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read.
The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.
After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR
Control Register.
The PWSEN bit saves power by dividing the MCI clock by 2
The command and the response of the card are clocked out with the rising edge of the MCI
Clock.
All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the MCI command register. The MCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register
are described in
Table 35-4.
Note:
Table 35-5.
CMD
CMD Index
CMD2
Field
CMDNB (command number)
RSPTYP (response type)
SPCMD (special command)
OPCMD (open drain command)
• Sequential commands: These commands initiate a continuous data stream. They are
• Block-oriented commands: These commands send a data block succeeded by CRC bits.
terminated only when a stop command follows on the CMD line. This mode reduces the
command overhead to an absolute minimum.
bcr means broadcast command with response.
S
T
ALL_SEND_CID Command Description
Fields and Values for MCI_CMDR Command Register
Type
bcr
Table 35-4
Host Command
Content
Argument
[31:0] stuff bits
and
CRC
Table
E
35-5.
Z
N
Resp
R2
ID
******
Cycles
Value
2 (CMD2)
2 (R2: 136 bits response)
0 (not a special command)
1
Abbreviation
ALL_SEND_CID
Z
S
PWSDIV
T
AT91SAM9261S
+ 1 when the bus is inactive.
Content
CID
Command
Description
Asks all cards to send
their CID numbers on
the CMD line
Z
Z
520
Z