UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 808
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIICA interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It
is also assumed that the INTIICA interrupt servicing only performs status transition processing, and that actual
data communication is performed by the main processing.
Therefore, data communication processing is performed by preparing the following three flags and passing
them to the main processing instead of INTIICA.
<1> Communication mode flag
<2> Ready flag
<3> Communication direction flag
This flag indicates the following two communication statuses.
• Clear mode:
• Communication mode: Status in which data communication is performed (from valid address detection
This flag indicates that data communication is enabled. Its function is the same as the INTIICA interrupt
for ordinary data communication.
processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag
is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted
without the flag being cleared (an address match is interpreted as a request for the next data).
This flag indicates the direction of communication. Its value is the same as TRC.
IICA
INTIICA
Setting
Status in which data communication is not performed
to stop condition detection, no detection of ACK from master, address
mismatch)
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
This flag is set by interrupt servicing and cleared by the main
Interrupt servicing
Setting
Data
Flag
Main processing
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