UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 168
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 168 of 1067
- Download datasheet (7Mb)
4.2.6 Port 5
using port mode register 5 (PM5). When the P50 to P53 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
166
P50/TI06/TO06
P51/TI07/TO07
P52/SLTI/SLTO
P53
Cautions 1.
Port 5 is a 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units
This port can also be used for timer I/O.
Reset signal generation sets port 5 to input mode.
Figures 4-10 to 4-12 show a block diagrams of port 5.
Note TI06/TO06 and TI07/TO07 are shared with P14 and P15, in products the 78K0R/IE3.
Remark n = 00, 01, 08 to 11
2.
To use P50/TI06/TO06 and P51/TI07/TO07 as a general-purpose port, set bits 6 and 7 (TO06
and TO07) of timer output register 0 (TO0) and bits 6 and 7 (TOE06 and TOE07) of timer
output enable register 0 (TOE0) to “0”, which is the same as their default status setting.
To use P52/SLTI/SLTO as a general-purpose port, check which timer I/O pin of which channel
n is selected in the input switching control register (ISC) setting (For details about the ISC
register, see 6.3 (24) Input switch control register (ISC). Also, set bit n (TOn) of timer output
register 0 (TO0) and bit n (TOEn) of timer output enable register 0 (TOE0) to “0”, which is the
same setting as in the initial state of each.
78K0R/IB3
−
−
√
√
(38-pin)
−
√
√
√
CHAPTER 4 PORT FUNCTIONS
User’s Manual U19678EJ1V1UD
78K0R/IC3
(44-pin)
−
√
√
√
(48-pin)
√
√
√
−
78K0R/ID3
√
√
√
−
78K0R/IE3
P50
P51
√
√
Note
Note
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