UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 130
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Address
F012AH
F012BH
F018AH
F018BH
F018CH
F018DH
F018EH
F018FH
F019AH
F019BH
F019CH
F019DH
F019EH
F019FH
F0134H
F0135H
F0180H
F0181H
F0182H
F0183H
F0184H
F0185H
F0186H
F0187H
F0188H
F0189H
F0190H
F0191H
F0192H
F0193H
F0194H
F0195H
F0196H
F0197H
F0198H
F0199H
128
Serial output enable register 0
Serial output level register 0
Timer counter register 00
Timer counter register 01
Timer counter register 02
Timer counter register 03
Timer counter register 04
Timer counter register 05
Timer counter register 06
Timer counter register 07
Timer mode register 00
Timer mode register 01
Timer mode register 02
Timer mode register 03
Timer mode register 04
Timer mode register 05
Timer mode register 06
Timer mode register 07
Special Function Register (SFR)
Name
Table 3-6. Extended SFR (2nd SFR) List (3/6)
SOE0L
SOL0L
TCR00
TCR01
TCR02
TCR03
TCR04
TCR05
TCR06
TCR07
TMR00
TMR01
TMR02
TMR03
TMR04
TMR05
TMR06
TMR07
CHAPTER 3 CPU ARCHITECTURE
−
−
Symbol
User’s Manual U19678EJ1V1UD
SOE0
SOL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Manipulable Bit Range
1-bit
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
8-bit
√
−
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
16-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Reset
After
√
√
√
√
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√
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√
√
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√
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