UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 378

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

376
Address: F0220H
Symbol
OPMR
(Cautions and Remark are given on the next page.)
OPM HPS HSM HDM ATS
HIS1
HIS0
The setting of HIS1 is enabled when HPS = 0.
The setting of HIS0 is enabled when HPS = 0.
ATS
ATS
15
3
0
0
1
1
1
0
0
1
1
0
1
0
1
TLSm
0
1
ATS
ATS
Sets the falling edge as valid.
Sets the rising edge as valid.
Sets the falling edge as valid.
Sets the rising edge as valid.
14
2
0
1
0
1
0
0
1
0
1
After reset: 0000H
Figure 7-10. Format of TAU Option Mode Register (OPMR) (2/2)
Generates an A/D trigger for the match interrupt during a down status period of the master
channel.
Generates an A/D trigger for the match interrupt during an up status period of the master
channel.
Generates an A/D trigger for the match interrupt during an up or a down status period of the
master channel
Generates an A/D trigger for the match interrupt during an up or a down status period of the
master channel + valley interrupt of the master channel
Generates an A/D trigger for the match interrupt during a down status period of the master
channel.
Generates an A/D trigger for the match interrupt during an up status period of the master
channel.
Generates an A/D trigger for the match interrupt during an up or a down status period of the
master channel
Generates an A/D trigger for the match interrupt during an up or a down status period of the
master channel + valley interrupt of the master channel
Performs forward output of timer output (TO0m).
Performs reverse output of timer output (TO0m).
13
CHAPTER 7 INVERTER CONTROL FUNCTIONS
12
11
3
R/W
User’s Manual U19678EJ1V1UD
ATS
10
Timer trigger signal 1 for A/D conversion selection
Timer trigger signal 0 for A/D conversion selection
2
OPM = 0: uses channel 9 for interrupt generation
OPM = 1: uses channel 5 for interrupt generation
OPM = 0: uses channel 8 for interrupt generation
OPM = 1: uses channel 1 for interrupt generation
ATS
TMOFF1 valid edge selection
TMOFF0 valid edge selection
9
1
Output reversal control (m = 2 to 7)
ATS
8
0
TLS
7
7
TLS
6
6
TLS
5
5
TLS
4
4
TLS
3
3
TLS
2
2
HIS
1
1
HIS
0
0