UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 695

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UPD78F1201MC-CAB-AX

Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1201MC-CAB-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Figure 13-67. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode)
Caution
After setting the SAU0EN bit of peripheral enable register 0 (PER0) to 1, be sure to set
serial clock select register 0 (SPS0) after 4 or more f
SMR0n, SCR0n:
SDR0n[15:9]:
SO0, SOE0:
Starting transmission/reception
Clearing SAU0EN bit of PER0
Setting SAU0EN bit of PER0
Starting CSI communication
Writing transmit data to
Setting transfer rate by
End of communication
Writing 1 to SS0n bit
Writing 1 to ST0n bit
SIOp (=SDR0n[7:0])
SIOp (=SDR0n[7:0])
Port manipulation
Transmission/reception
Transfer end interrupt
SPS0 register
Yes
Yes
register to 1
register to 0
completed?
generated?
Reading
register
Setting communication
Setting 0000000B
Setting output
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
No
No
Specify the initial settings while the
SE0n bit of serial channel enable
status register 0 (SE0) is 0 (operation
is stopped).
CLK
clocks have elapsed.
693

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