UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 640

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.2 Stopping the operation by channels
638
The stopping of the operation by channels is set using each of the following registers.
SOE0
SE0
SO0
ST0
(a) Serial channel stop register 0 (ST0) … This register is a trigger register that is used to enable
(b) Serial Channel Enable Status Register 0 (SE0) … This register indicates whether data
Note
Remark
(c) Serial output enable register 0 (SOE0) … This register is a register that is used to enable or stop
(d) Serial output register 0 (SO0) …This register is a buffer register for serial output of each channel.
stopping communication/count by each channel.
transmission/reception operation of each channel is enabled or stopped.
output of the serial communication operation of each channel.
*
*
*
* When using pins corresponding to each channel as port function pins, set the corresponding CKO0n and SO0n bits to “1”.
With a channel whose operation is stopped, the value of CKO0n bit of the SO0 register can be set by software.
1: Serial clock output value is “1”
Because ST0n bit is a trigger bit, it is cleared immediately when SE0n = 0.
The SE0 register is a read-only status register, whose operation is stopped by using the ST0 register.
For channel n, whose serial output is stopped, the SO0n bit value of the SO0 register can be set by software.
15
15
15
15
0
0
0
0
Figure 13-23. Each Register Setting When Stopping the Operation by Channels
44-pin and 48-pin of 78K0R/IC3, 78K0R/ID3, and 78K0R/IE3 only
n: Channel number (n = 0 to 3)
14
14
14
14
0
0
0
0
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
13
13
13
13
0
0
0
0
1: Clears SE0n bit to 0 and stops the communication operation
12
12
12
12
0
0
0
0
11
11
11
11
0
0
1
0
CHAPTER 13 SERIAL ARRAY UNIT
CKO02
0/1
10
10
10
10
0
0
0
0: Stops output by serial communication operation
User’s Manual U19678EJ1V1UD
0/1
CKO01
0
0
9
9
0
9
9
Note
0/1
CKO00
0
8
0
8
8
8
0
Note
1: Serial data output value is “1”
0
7
0
7
7
0
7
0
0: Operation stops
0
6
0
0
6
6
0
6
0
5
0
0
5
0
5
5
0
0
4
0
4
0
4
4
SE03
ST03
0/1
0/1
3
3
3
1
3
0
SOE02
SO02
ST02
SE02
0/1
0/1
0/1
0/1
2
2
2
2
0/1
0/1
SOE01
SO01
ST01
SE01
0/1
0/1
1
1
1
1
Note
Note
SOE00
SO00
ST00
SE00
0/1
0/1
0/1
0/1
0
0
0
0