UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 748

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UPD78F1201MC-CAB-AX

Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1201MC-CAB-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
746
SCL10 output
SDA10 output
(2) Processing flow
SDA10 input
SDA10 output
SCL10 output
SDA10 input
register 02
INTIIC10
register 02
TXE02,
RXE02
(a) When starting data reception
(b) When receiving last data
SOE02
SDR02
TSF02
INTIIC10
TXE02,
RXE02
SE02
ST02
SOE02
SDR02
Shift
TSF02
SS02
SE02
ST02
Shift
D2
Output is enabled by serial
TXE02 = 1 / RXE02 = 0
communication operation
“H”
Dummy data (FFH)
D1
Shift operation
D0
ACK
Figure 13-101. Timing Chart of Data Reception
Receive data
CHAPTER 13 SERIAL ARRAY UNIT
D7
User’s Manual U19678EJ1V1UD
D7
D6
D6
Output is stopped by serial communication operation
TXE02 = 0 / RXE02 = 1
D5
D5
Dummy data (FFH)
Dummy data (FFH)
TXE02 = 0 / RXE02 = 1
Reception of last byte
D4
D4
Shift operation
Shift operation
D3
D3
D2
D2
D1
D1
D0
NACK
D0
IIC operation stop
ACK
SO02 bit
manipulation
Step condition
Receive data
Receive data
CKO02 bit
manipulation
SO02 bit
manipulation

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