UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 776
UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(4) IICA flag register (IICF)
This register sets the operation mode of I
IICF can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are
read-only.
The IICRSV bit can be used to enable/disable the communication reservation function.
STCEN can be used to set the initial value of the IICBSY bit.
IICRSV and STCEN can be written only when the operation of I
register 0 (IICCTL0) = 0). When operation is enabled, the IICF register can be read.
Reset signal generation clears this register to 00H.
Remark
Condition for clearing (ACKD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (STD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (SPD = 0)
• At the rising edge of the address transfer byte’s first
• When IICE changes from 1 to 0 (operation stop)
• Reset
ACKD
following address transfer
clock following setting of this bit and detection of a
start condition
STD
SPD
0
1
0
1
0
1
LREL:
IICE:
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Figure 14-7. Format of IICA Status Register (IICS) (3/3)
Bit 6 of IICA control register 0 (IICCTL0)
Bit 7 of IICA control register 0 (IICCTL0)
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD = 1)
• After the SDA0 line is set to low level at the rising
Condition for setting (STD = 1)
• When a start condition is detected
Condition for setting (SPD = 1)
• When a stop condition is detected
edge of SCL0’s ninth clock
2
C is disabled (bit 7 (IICE) of IICA control
2
C bus.
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