UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 790

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.7 Canceling wait
resumed.
register 0 (IICCTL0) to 1.
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IICA.
so that the wait state can be canceled.
IICCTL0, so that the wait state can be canceled.
788
The I
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to IICA.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL) of IICA control
To generate a restart condition after canceling a wait state, set bit 1 (STT) of IICCTL0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT) of IICCTL0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IICA after canceling a wait state by setting WREL to 1, an incorrect value may be
In addition to the above, communication is stopped if IICE is cleared to 0 when communication has been aborted,
If the I
Note Master only
Caution
2
C usually cancels a wait state by the following processing.
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL) of
If a processing to cancel a wait state is executed when WUP = 1, the wait state will not be
canceled.
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
2
C cancels the wait state and communication is
Note
Note