UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 413

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark m = 02 to 07
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Figure 7-32. Operation Procedure When Triangular Wave PWM Output Function Is Used (1/2)
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMR00 and TMRm registers of each channel to
be used (determines operation mode of channels).
An interval (period) value is set to the TDR00 register of
the master channel, and a duty factor is set to the
TDRm register of the slave channel.
Sets the master channel.
Sets the slave channel.
Sets the TOE00 and TOEm bits to 1 and enables
operation of TO00 and TOm.
Clears the port register and port mode register to 0.
Sets the TOE00 (master) and TOEm (slave) bits to 1
(only when operation is resumed).
The TS00 (master) and TSm (slave) bits of the TS0
register are set to 1 at the same time.
The set value of the TDR00 (master) register must be
changed during an up status period.
The set value of the TDRm (slave) register can be
changed.
The TCR00 and TCRm registers can always be read.
The TSRm (slave) register can always be read.
Determines the clock frequencies of CK00 and CK01.
Sets the TOM00 bit of the TOM0 register to 0 (master
channel output mode).
Sets the TOMm bit of the TOM0 register to 1 (slave
channel output mode).
Sets the TOTm bit of the TOT0 register to 1
(triangular wave PWM output).
Sets the TOLm bit to 0 (positive logic output).
Sets the TOm bit and determines default level of the
TOm output.
The TS00 and TSm bits automatically return to 0
because they are trigger bits.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-on status. Each channel stops operating.
The TOn default setting level is output when the port mode
register is in output mode and the port register is 0.
Power-off status
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO00 and TOm pins go into Hi-Z output states.
TO00 and TOm do not change because channel stops
operating.
The TO00 and TOm pins output the TO00 and TOm set levels.
TE00 = 1, TEm = 1
At the master channel, a period is generated and count
operation of the slave channel is controlled. TCR00 loads
the value of TDR00 and counts down. When the count value
reaches TCR00 = 0000H, INTTM00 is generated. At the
same time, the value of the TDR00 register is loaded to
TCR00, and the counter starts counting down again.
At the slave channel, INTTM00 of the master channel is
used as the trigger to switch counting down and counting up.
INTTMm is generated upon detection of TCRm = 0001H and
TOm outputs a triangular wave PWM.
At the master channel, TCR00 loads the value of TDR00
again and count operation is continued by the generation of
INTTM00 during an up status.
After that, the above operation is repeated.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
When the master and slave channels starts counting and
the MD000 bit of the TMR00 register is 1, INTTM00 is
generated.
Hardware Status
411