UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 209
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Note 1
(6) A/D port configuration register (ADPC)
Symbol
Address: F0017H
ADPC
This register switches the P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 pins to digital I/O of port or
analog input of A/D converter.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Note 1
Note 1
Note 2
Notes 1. Setting permitted
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode
Note 1
Note 2
Note 1
7
0
2. Setting prohibited
Note 1
Note 2
Note 1
After reset: 10H
2. Do not set the pin that is set by ADPC as digital I/O by ADS.
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 are set as analog inputs in the order
Note 1
Note 2
Note 1
register 2 and 15 (PM2, PM15).
of P153/ANI11, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration
register (ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 as
analog inputs, start designing from P153/ANI11.
Figure 4-43. Format of A/D Port Configuration Register (ADPC)
6
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Other than the above
0
0
0
0
0
0
0
0
1
1
1
1
0
R/W
0
0
0
0
1
1
1
1
0
0
0
0
0
5
0
CHAPTER 4 PORT FUNCTIONS
0
0
1
1
0
0
1
1
0
0
1
1
0
User’s Manual U19678EJ1V1UD
0
1
0
1
0
1
0
1
0
1
0
1
0
ADPC4
Setting prohibited
4
A
A
A
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
D
Port 15
D
ADPC3
A
A
A
A
A
A
A
A
A
A
D
D
D
Analog input (A)/digital I/O (D) switching
3
D
D
D
D
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
D
D
D
ADPC2
A
A
A
A
A
A
A
D
D
D
D
D
D
2
A
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
Port 2
ADPC1
1
D
D
D
D
D
D
D
A
A
A
A
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
ADPC0
A
A
D
D
D
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
D
D
D
D
A
207
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