UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 595

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.3 Trigger mode selection
by the ADM1 register.
(1) Software trigger mode
(2) Timer trigger mode (hardware trigger mode)
The following two trigger modes that set the A/D conversion start timing are provided. These trigger modes are set
• Software trigger mode
• Timer trigger mode (hardware trigger mode)
This mode is used to start A/D conversion of the analog input channels (ANI0 to ANI11, PGAO), which have been
selected by the analog input channel specification register (ADS), by setting ADCS to 1.
A/D conversion is repeatedly performed as long as the ADCS bit is not cleared to 0, after completion of A/D
conversion.
If the ADM, ADM1, or ADS register is written during conversion, A/D conversion is aborted. In this case, A/D
conversion is started again from the beginning in the select mode, and A/D conversion is started again from scan
0 in the scan mode.
This mode is used to start A/D conversion of the analog input channels (ANI0 to ANI11, PGAO), which have been
selected by the analog input channel specification register (ADS), by setting ADCS to 1 and detecting timer
trigger signals 0 and 1.
A/D conversion is repeatedly performed as long as the ADCS bit is not cleared to 0, after completion of A/D
conversion.
If a timer trigger signal is generated during A/D conversion or if the ADM, ADM1, or ADS register is written during
conversion, A/D conversion is aborted. In this case, A/D conversion is started again from the beginning in the
select mode, and A/D conversion is started again from scan 0 in the scan mode.
Remarks
ANI0 to ANI5
ANI0 to ANI7
ANI0 to ANI9
ANI0 to ANI10 : 48-pin products of 78K0R/IC3 and 78K0R/ID3
ANI0 to ANI11 : 78K0R/IE3
: 78K0R/IB3
: 38-pin products of 78K0R/IC3
: 44-pin products of 78K0R/IC3
CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
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