UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 596
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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12.4.4 A/D converter operation modes
(1) Select mode
594
A/D conversion
The select mode and scan mode are provided as the A/D converter operation modes.
One analog input specified by the analog input channel specification register (ADS), while the ADMD bit of A/D
converter mode register (ADM) is 0, is A/D converted.
When A/D conversion is complete, the conversion result is stored in the A/D conversion result register (ADCR)
and the A/D conversion end interrupt request signal (INTAD) is generated.
If anything is written to ADM, ADM1, or ADS during conversion, A/D conversion is aborted. In this case, A/D
conversion is started again from the beginning, regardless of being in the software trigger mode or timer trigger
mode (hardware trigger mode).
operation
ADCRH
ADCR,
INTAD
ANI1
Conversion start
Set ADCS bit = 1
Data 1
Data 1
(ANI1)
Figure 12-15. Example of Select Mode Operation Timing
Data 1
(ANI1)
CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
Data 2
Data 2
(ANI1)
Data 2
(ANI1)
Data 3
Data 3
(ANI1)
Data 3
(ANI1)
Data 4
Data 4
(ANI1)
Conversion stop
Set ADCS bit = 0
Data 4
(ANI1)
Conversion end
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