UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 653
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UPD78F1201MC-CAB-AX
Manufacturer Part Number
UPD78F1201MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1201MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(1) Register setting
SCR0n
SMR0n
SDR0n
SO0
(a) Serial mode register 0n (SMR0n)
(d) Serial output register 0 (SO0) … Sets only the bits of the target channel.
Remark
(b) Serial communication operation setting register 0n (SCR0n)
(c) Serial data register 0n (SDR0n) (lower 8 bits: SIOp)
Note
Figure 13-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O
TXE0n
CKS0n
Selection of the data and clock
phase (For details about the
setting, see 13.3 Registers
Controlling Serial Array Unit.)
0/1
Operation clock (f
0: Prescaler output clock CK00 set by SPS0 register
1: Prescaler output clock CK01 set by SPS0 register
15
15
15
15
0
0
n: Channel number (n = 0 to 2) (n = 2 (78K0R/IB3 and 38-pin products of 78K0R/IC3), n = 0 to 2
(44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3, and 78K0R/IE3))
p: CSI number (p = 00, 01, 10) (p = 10 (78K0R/IB3 and 38-pin products of 78K0R/IC3), p = 00, 01,
10 (44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3, and 78K0R/IE3))
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
RXE0n
CSI00 and CSI01 are only available in the 44-pin and 48-pin products of the 78K0R/IC3 and in the
78K0R/ID3 and 78K0R/IE3.
CCS0n
14
1
14
14
14
0
0
(Operation clock (f
: Setting is fixed in the CSI master reception mode,
DAP0n
0/1
13
13
13
13
0
0
Baud rate setting
MCK
CKP0n
0/1
12
) of channel n
12
12
12
0
0
MCK
) division setting)
11
0
11
11
11
0
1
CHAPTER 13 SERIAL ARRAY UNIT
(CSI00
EOC0n
CKO02
10
0/1
10
0
10
10
0
User’s Manual U19678EJ1V1UD
PTC0n1
0/1
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
CKO01
Note
9
0
0
9
9
9
, CSI01
Note
PTC0n0
0/1
STS0n
CKO00
0
8
8
0
8
8
0
Note
Note
DIR0n
0/1
, CSI10) (1/2)
Communication starts when these bits are 1 if the clock
phase is forward (the CKP0n bit of the SCR0n register =
0). If the clock phase is reversed (CKP0n bit = 1),
communication starts when these bits are 0.
7
0
0
7
7
7
SIS0n0
0
6
0
0
6
6
6
SLC0n1
: Setting disabled (set to the initial value)
5
0
5
1
5
0
5
(Write FFH as dummy data.)
SLC0n0
Receive data
0
4
4
0
4
0
4
Interrupt sources of channel n
SIOp
0
0
1: Buffer empty interrupt
3
3
3
1
3
0: Transfer end interrupt
Setting of data length
DLS0n2
MD0n2
0: 7-bit data length
1: 8-bit data length
SO02
2
2
0
1
×
2
2
DLS0n1
MD0n1
SO01
×
1
0
1
1
1
1
Note
DLS0n0
MD0n0
SO00
0/1
×
0
0
0
0
0
651
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