UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 84

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0/Kx2-L
(1) Vector table area
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Vector Table
The internal program memory space is divided into the following areas.
Remark √: Mounted, −: Not mounted
Address
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon
reset or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
000AH
000CH
000EH
001AH
001CH
001EH
002AH
002CH
002EH
003AH
003CH
003EH
0000H
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0020H
0022H
0024H
0026H
0028H
0030H
0032H
0034H
0036H
0038H
RESET input,
POC, LVI, WDT
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTSRE6
INTSR6
INTST6
INTCSI10
INTCSI11
INTTMH1
INTTMH0
INTTM50
INTTM000
INTTM010
INTAD
INTP6
INTRTCI
INTTM51
INTKR
INTRTC
INTP7
INTP8
INTIICA0
INTCSI11
INTP9
INTP10
INTP11
BRK
Interrupt Source
16 Pins
KY2-L
78K0/
√
√
√
√
−
−
−
−
√
√
√
−
−
√
−
−
√
√
√
−
−
√
−
−
−
−
√
−
−
−
−
√
20 Pins
Table 3-4. Vector Table
√
√
√
√
√
√
−
−
√
√
√
−
−
√
−
−
√
√
√
−
−
√
−
−
−
−
√
−
−
−
−
√
78K0/KA2-L
25 Pins
√
√
√
−
√
√
√
√
√
√
√
−
√
√
−
−
√
√
√
−
−
√
−
−
−
−
√
−
−
−
−
√
32 Pins
√
√
√
−
√
√
√
√
√
√
√
−
√
√
−
−
√
√
√
−
−
√
−
−
−
−
√
−
−
−
−
√
CHAPTER 3 CPU ARCHITECTURE
30 Pins
KB2-L
78K0/
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
−
√
−
−
−
−
√
−
−
√
√
√
40 Pins
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
√
√
√
√
−
−
√
√
√
√
√
√
78K0/KC2-L
44 Pins
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
√
√
√
√
−
√
√
√
√
√
√
√
48 Pins
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
70