UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 425
UPD78F0551MA-FAA-AX
Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0551MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2-L
(3) 8-bit A/D conversion result register L (ADCRL)
(4) 8-bit A/D conversion result register H (ADCRH)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
This register is an 8-bit register that stores the A/D conversion result. The lower 8 bits of 10-bit resolution are stored.
ADCRL can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
2. If data is read from ADCRL, a wait cycle is generated. Do not read data from ADCRL when the
2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCRL
may become undefined. Read the conversion result following conversion completion before
writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause an
incorrect conversion result to be read.
peripheral hardware clock (f
WAIT.
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCRH
may become undefined. Read the conversion result following conversion completion before
writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause an
incorrect conversion result to be read.
peripheral hardware clock (f
WAIT.
Address: FF08H
Address: FF0DH
ADCRH
Symbol
ADCRL
Symbol
Figure 12-6. Format of 8-Bit A/D Conversion Result Register L (ADCRL)
Figure 12-7. Format of 8-Bit A/D Conversion Result Register (ADCRH)
7
7
After reset: 00H
After reset: 00H
6
6
PRS
PRS
5
) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
5
) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
R
R
4
4
3
3
2
2
CHAPTER 12 A/D CONVERTER
1
1
0
0
411
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