UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 682

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0/Kx2-L
(2) When LVI is ON upon power application (option byte: LVISTART = 1)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
Remark V
V
V
V
POR
oscillation clock (f
(when X1 oscillation
PDR
Internal reset signal
Internal high-speed
LVI
CPU
system clock (f
= 1.91 V (TYP.)
= 1.61 V (TYP.)
= 1.59 V (TYP.)
Supply voltage
High-speed
is selected)
2.
3.
1.8 V
Operation
LOW-VOLTAGE DETECTOR).
V
V
(V
stops
Note 1
V
The operation guaranteed range is 1.8 V ≤ V
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
The internal high-speed oscillation clock, high-speed system clock or subsystem clock can be selected as
the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation
stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the
stabilization time.
The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and starting
normal operation.
• When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is less than 3.7 ms:
• When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is greater than 3.7 ms:
LVI
POR
PDR
0 V
DD
LVI
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
XH
IH
)
)
)
A POC processing time of about 1.0 to 3.8 ms is required between reaching 1.59 V (TYP.) and starting
normal operation.
A reset processing time of about 12 to 51
normal operation.
:
: POC power supply fall detection voltage
: POC power supply rise detection voltage
LVI detection voltage
Note 3
Wait for oscillation
accuracy stabilization
(102 to 407 s)
POC processing time
(0.93 to 3.7 ms)
oscillation clock)
(internal high-speed
Reset processing time
(12 to 51 s)
Set LVI to be
used for reset
Normal operation
specified by software
Starting oscillation is
Note 2
and Low-Voltage Detector (2/2)
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
(102 to 407 s)
used for interrupt
Reset processing time
(12 to 51 s)
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
DD
μ
s is required between reaching 1.91 V (TYP.) and starting
≤ 5.5 V. To make the state at lower than 1.8 V reset state
specified by software
Starting oscillation is
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Note 2
(oscillation
Reset
period
stop)
Note 3
Wait for oscillation
accuracy stabilization
(102 to 407 s)
POC processing time
(0.93 to 3.7 ms)
oscillation clock)
Reset processing time
(12 to 51 s)
(internal high-speed
used for reset
Set LVI to be
Normal operation
specified by software
Starting oscillation is
Note 2
Operation stops
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