UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 369
UPD78F0551MA-FAA-AX
Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0551MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 369 of 822
- Download datasheet (6Mb)
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
<1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer counter
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values
<5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, an inactive level is
<6> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM output to
(TOLEV1 = 0)
Count clock
counter Hn
8-bit timer
INTTMH1
clock to count up. At this time, PWM output outputs an inactive level.
count clock.
Hn is cleared, an active level is output, and the INTTMHn signal is output.
of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the
CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when the
value is transferred to the register. If a match signal is generated within three count clocks, the changed value
cannot be transferred to the register.
output. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
an inactive level.
Remark 78K0/KY2-L, 78K0/KA2-L: n = 1
CMP01
CMP11
TMHE1
TOH1
00H 01H 02H
78K0/KB2-L, 78K0/KC2-L: n = 0, 1
<1>
(e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H)
02H
Figure 8-15. Operation Timing in PWM Output Mode (4/4)
80H
<2>
A5H 00H 01H 02H 03H
02H (03H)
<3>
<2>’
<4>
A5H
03H
CHAPTER 8 8-BIT TIMERS H0 AND H1
A5H 00H 01H 02H 03H
<5>
A5H 00H
<6>
355
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