UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 523

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5.4 Acknowledge (ACK)
it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected
can be checked by using bit 2 (ACKD0) of the IICA status register 0 (IICAS0).
does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission.
If ACK is not returned, the possible causes are as follows.
(TRC0) of the IICAS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set
ACKE0 to 1 for reception (TRC0 = 0).
must inform the master, by clearing ACKE0 to 0, that it will not receive any more data.
ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more
data (transmission will be stopped).
an address other than that of the local address is received, ACK is not generated (NACK).
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side,
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave
<1> Reception was not performed normally.
<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDAA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IICA control register 0 (IICACTL0) to 1. Bit 3
If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the slave
When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that
When the local address is received, ACK is automatically generated, regardless of the value of the ACKE0 bit. When
When an extension code is received, ACK is generated if the ACKE0 bit is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
• When 8-clock wait state is selected (bit 3 (WTIM0) of IICACTL0 register = 0):
• When 9-clock wait state is selected (bit 3 (WTIM0) of IICACTL0 register = 1):
By setting the ACKE0 bit to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock
of the SCLA0 pin.
ACK is generated by setting the ACKE0 bit to 1 in advance.
SDAA0
SCLA0
A6
1
A5
2
Figure 15-19. ACK
A4
3
A3
4
A2
5
A1
6
CHAPTER 15 SERIAL INTERFACE IICA
A0
7
R/W
8
ACK
9
509