UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 427

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
78K0/Kx2-L
(6) A/D port configuration registers 0, 1
(a) 78K0/KY2-L
(b) 78K0/KA2-L (20-pin products)
(c) 78K0/KA2-L (25-pin products)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Cautions 1. Be sure to clear bits 4, 5, and 7 to “0”.
ADPC0 switches the P20/AMP0-/ANI0 to P27/ANI7 pins to digital I/O or analog I/O of port. Each bit of ADPC0
corresponds to a pin of port 2 and can be specified in 1-bit units.
ADPC1 switches the P10/AMP1-/ANI8 to P12/AMP1+/ANI10 or P70/ANI8 to P72/ANI10 pins to digital I/O or analog
I/O of port. Each bit of ADPC1 corresponds to a pin of P10 to P12 in port 1 or P70 to P72 in port7 and can be
specified in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears ADPC0 to 00H, sets ADPC1 of 78K0/KA2-L (32-pin products) to 00H, and sets ADPC1
of 78K0/KB2-L and 78K0/KC2-L to 07H.
Note
Address: FF2EH
Address: FF2EH
Address: FF2EH
Symbol
ADPC0
Symbol
ADPC0
Symbol
ADPC0
78K0/KA2-L (32-pin products), 78K0/KB2-L, and 78K0/KC2-L only
2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 1, 2,
3. Set ADS after PGA operation setting when selecting the PGA output signal as analog input. Set
4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the peripheral
Figure 12-9. Format of A/D Port Configuration Registers 0, 1 (ADPC0, ADPC1) (1/3)
7 (PM1, PM2, PM7).
ADS after single AMP operation setting when selecting the operational amplifier output signal as
analog input (refer to CHAPTER 13 OPERATIONAL AMPLIFIERS).
hardware clock (f
7
0
7
0
7
0
After reset: 00H
After reset: 00H
After reset: 00H
ADPCS6
PRS
6
0
6
0
6
) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT.
Note
R/W
R/W
R/W
ADPCS5
ADPCS5
(ADPC0, ADPC1
5
0
5
5
ADPCS4
ADPCS4
4
0
4
4
Note
)
ADPCS3
ADPCS3
ADPCS3
3
3
3
ADPCS2
ADPCS2
ADPCS2
CHAPTER 12 A/D CONVERTER
2
2
2
ADPCS1
ADPCS1
ADPCS1
1
1
1
ADPCS0
ADPCS0
ADPCS0
0
0
0
413