UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 361

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
8.4 Operation of 8-Bit Timers H0 and H1
8.4.1 Operation as interval timer/square-wave output
generated and the 8-bit timer counter Hn is cleared to 00H.
CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
output from TOHn.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
TMHMDn
When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is
Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and the
By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is
<1> Set each register.
<2> Count operation starts when TMHEn = 1.
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn
Remarks 1. For the setting of the output pin, refer to 8.3 (4) Port mode register 0 (PM0), port mode register 1
Setting
(i) Setting timer H mode register n (TMHMDn)
(ii) CMP0n register setting
and the 8-bit timer counter Hn is cleared to 00H.
to 0.
TMHEn
The interval time is as follows if N is set as a comparison value.
• Interval time = (N +1)/f
2. For how to enable the INTTMHn signal interrupt, refer to CHAPTER 17 INTERRUPT FUNCTIONS.
3. 78K0/KY2-L, 78K0/KA2-L: n = 1
0
(PM1), port mode register 3 (PM3).
78K0/KB2-L, 78K0/KC2-L: n = 0, 1
Figure 8-12. Register Setting During Interval Timer/Square-Wave Output Operation
CKSn2
0/1
CKSn1
0/1
CNT
CKSn0
0/1
TMMDn1
0
TMMDn0 TOLEVn
0
0/1
CHAPTER 8 8-BIT TIMERS H0 AND H1
TOENn
0/1
Timer output setting
Default setting of timer output level
Interval timer mode setting
Count clock (f
Count operation stopped
CNT
) selection
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