UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 658
UPD78F0551MA-FAA-AX
Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0551MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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- Download datasheet (6Mb)
78K0/Kx2-L
Remarks 1.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event counter 00
8-bit timer/event
counter
8-bit timer
Real-time counter (RTC)
Watchdog timer
Clock output
A/D converter
Operational amplifiers 0, 1
Serial interface
Key interrupt
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
IL
2.
HALT Mode Setting
f
f
f
The functions mounted depend on the product.
Functions.
IH
EXCLK
EXCLKS
:
UART6
CSI10
CSI11
IICA
: External main system clock,
: External subsystem clock,
f
f
f
f
f
Internal high-speed oscillation clock,
IH
X
EXCLK
XT
EXCLKS
50
51
H0
H1
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable
Operable. However, operation disabled when peripheral hardware clock (f
Operable
When CPU Is Operating on XT1 Clock (f
Table 19-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
f
f
f
X
XT
IL
: X1 clock
: Internal low-speed oscillation clock
: XT1 clock
Refer to 1.4
XT
)
Status before HALT mode was set is retained
Operation continues (cannot be stopped)
CHAPTER 19 STANDBY FUNCTION
When CPU Is Operating on External
Block Diagram and 1.5
Subsystem Clock (f
PRS
) is stopped.
EXCLKS
)
Outline of
644
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