UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 661

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
19.2.2 STOP mode
(1) STOP mode setting and operating statuses
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
The operating statuses in the STOP mode are shown below.
Notes 1. 78K0/KC2-L only
Subsystem clock
(XT1 oscillation)
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
Status of CPU
2. Oscillation stabilization time is not required when using the external subsystem clock (f
×: don’t care
Reset signal
subsystem clock.
Maskable interrupt
request
Reset
Table 19-2. Operation in Response to Interrupt Request in HALT Mode
Release Source
(subsystem clock)
Normal operation
(3) When subsystem clock is used as CPU clock
Figure 19-4. HALT Mode Release by Reset (2/2)
instruction
Oscillates
HALT
MK××
0
0
0
0
0
1
−
HALT mode
PR××
0
0
1
1
1
×
−
IE
0
1
0
×
1
×
×
Oscillation
stopped
period
Reset
ISP
Starting XT1 oscillation is
×
×
1
0
1
×
×
(12 to 51 s)
processing
Oscillation
specified by software.
Reset
stopped
CHAPTER 19 STANDBY FUNCTION
HALT mode held
Reset processing
Next address
instruction execution
Interrupt servicing
execution
Next address
instruction execution
Interrupt servicing
execution
Normal operation mode
Note1
(internal high-speed
oscillation clock)
Oscillates
Operation
Oscillation stabilization time
(measure by the user)
Note 2
EXCLKS
) as the
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