UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 380

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
9.4 Operation of Watchdog Timer
9.4.1 Controlling operation of watchdog timer
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
1.
2.
3.
4.
5.
Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
When the watchdog timer is used, its operation is specified by the option byte (0080H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, refer to
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for
After a reset release, the watchdog timer starts counting.
By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the option
byte, the watchdog timer is cleared and starts counting again.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE is
written during a window close period, an internal reset signal is generated.
If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
A internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If the instruction is fetched from an area not set by the IMS register (detection of an invalid check during a CPU
• If the CPU accesses an area not set by the IMS register (excluding FB00H to FFFFH) by executing a read/write
counter starts operating after a reset release) (for details, refer to CHAPTER 24).
9.4.2 and CHAPTER 24).
details, refer to 9.4.3 and CHAPTER 24).
program loop)
instruction (detection of an abnormal access during a CPU program loop)
WDTON
0
1
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH).
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
different from the overflow time set by the option byte by up to 2/f
Counter operation disabled (counting stopped after reset), illegal access detection operation disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Operation Control of Watchdog Timer Counter/Illegal Access Detection
CHAPTER 9 WATCHDOG TIMER
IL
seconds.
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