UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 813

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
2nd Edition
Remark “Classification” in the above table classifies revisions as follows.
Edition
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Modification of Figure 4-45 Format of A/D Port Configuration Register 0 (ADPC0)
Modification of Figure 4-46 Format of A/D Port Configuration Register 1 (ADPC1)
(78K0/KB2-L and 78K0/KC2-L Only)
Modification of PM×× and P×× value of P125 pin in Table 4-12 Settings of Port Mode
Register and Output Latch When Using Alternate Function (78K0/KY2-L) to Table 4-
15 Settings of Port Mode Register and Output Latch When Using Alternate Function
(78K0/KC2-L)
Modification of Table 4-14 Settings of Port Mode Register and Output Latch When
Using Alternate Function (78K0/KB2-L) (1/2) and Table 4-15 Settings of Port Mode
Register and Output Latch When Using Alternate Function (78K0/KC2-L) (1/3)
Modification of Figure 5-2 Block Diagram of Clock Generator (78K0/KC2-L)
Modification of and addition of Caution 3 to Figure 5-4 Format of Clock Operation Mode
Select Register (OSCCTL) (78K0/KC2-L)
Modification of Caution 1 in 5.4 System Clock Oscillator
Modification of Figure 6-9 Format of Prescaler Mode Register 00 (PRM00)
Modification of Figure 6-13 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 6-17 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 6-20 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 6-30 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 6-38 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 6-41 (d) Prescaler mode register 00 (PRM00) and (f) 16-bit
capture/compare register 000 (CR000)
Modification of Figure 6-44 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 6-51 (d) Prescaler mode register 00 (PRM00)
Modification of Figure 7-2 Block Diagram of 8-bit Timer 51 (78K0/KY2-L, 78K0/KA2-L)
and Figure 7-3 Block Diagram of 8-bit Timer 51 (78K0/KB2-L, 78K0/KC2-L)
Modification of Figure 7-7 Format of Timer Clock Selection Register 51 (TCL51)
Deletion of Caution 2 from and modification of Remark in Table 9-4 Setting Window
Open Period of Watchdog Timer
• Modification of the number of channels in the 78K0/KB2-L and 78K0/KC2-L
• Addition of 8-bit A/D conversion result register L (ADCRL)
Modification of Table 12-2 A/D Conversion Time Selection
Partial deletion of description in 12.3 (2) 10-bit A/D conversion result register (ADCR)
Modification of Figure 12-9 Format of A/D Port Configuration Register 0 (ADPC0)
Modification of Figure 12-10 Format of A/D Port Configuration Register 1 (ADPC1)
(78K0/KB2-L and 78K0/KC2-L Only)
Description
APPENDIX C REVISION HISTORY
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 16-BIT
TIMER/EVENT
COUNTER 00
CHAPTER 7 8-BIT
TIMER/EVENT
COUNTERS 50 AND
51
CHAPTER 9
WATCHDOG TIMER
CHAPTER 12 A/D
CONVERTER
Chapter
(2/8)
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