UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 236
UPD78F0551MA-FAA-AX
Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0551MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 236 of 822
- Download datasheet (6Mb)
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(4) Example of setting procedure when stopping the high-speed system clock
<2> Setting the high-speed system clock as the main system clock (MCM register)
<3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register)
The high-speed system clock can be stopped in the following two ways.
• Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is used)
• Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used)
(a) To execute a STOP instruction
<1> Setting to stop peripheral hardware
<2> Setting the X1 clock oscillation stabilization time after standby release
<3> Executing the STOP instruction
When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and
peripheral hardware clock.
Caution If the high-speed system clock is selected as the main system clock, a clock other than the
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division
ratio, use PCC0, PCC1, and PCC2.
XSEL
CSS
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be
used in STOP mode, refer to CHAPTER 19 STANDBY FUNCTION).
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is
stopped (the input of the external clock is disabled).
1
0
high-speed system clock cannot be set as the peripheral hardware clock.
MCM0
PCC2
1
0
0
0
0
1
Other than above
High-speed system clock (f
Selection of Main System Clock and Clock Supplied to Peripheral Hardware
PCC1
0
0
1
1
0
Main System Clock (f
PCC0
0
1
0
1
0
XH
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
XP
)
)
/2 (default)
/2
/2
/2
2
3
4
CPU Clock (f
High-speed system clock (f
Peripheral Hardware Clock (f
CHAPTER 5 CLOCK GENERATOR
CPU
) Selection
XH
)
PRS
)
222
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