UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 539

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5.15 Cautions
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(1) When STCEN (bit 1 of IICA flag register 0 (IICAF0)) = 0
(2) When STCEN = 1
(3) If other I
(4) Setting the STT0 and SPT0 bits (bits 1 and 0 of the IICACTL0 register) again after they are set and before they are
(5) When transmission is reserved, set SPIE0 (bit 4 of the IICACTL0 register) to 1 so that an interrupt request is
Immediately after I
IICAF0 register) = 1) is recognized regardless of the actual bus status. When changing from a mode in which no
stop condition has been detected to a master device communication mode, first generate a stop condition to
release the bus, then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register 1 (IICACTL1).
<2> Set bit 7 (IICE0) of IICA control register 0 (IICACTL0) to 1.
<3> Set bit 0 (SPT0) of IICACTL0 to 1.
Immediately after I
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of the IICA control register 0
(IICACTL0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
If I
low and the SCLA0 pin is high, the macro of I
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I
<1> Clear bit 4 (SPIE0) of the IICACTL0 register to 0 to disable generation of an interrupt request signal
<2> Set bit 7 (IICE0) of the IICACTL0 register to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of the IICACTL0 register to 1 before ACK is returned (4 to 80 clocks after setting the IICE0
cleared to 0 is prohibited.
generated when the stop condition is detected. Transfer is started when communication data is written to the IICA
shift register (IICA) after the interrupt request is generated. Unless the interrupt is generated when the stop
condition is detected, the device stops in the wait state because the interrupt request is not generated when
communication is started. However, it is not necessary to set the SPIE0 bit to 1 when the MSTS0 bit (bit 7 of the
IICA status register (IICAS0)) is detected by software.
2
C operation is enabled and the device participates in communication already in progress when the SDAA0 pin is
(INTIICA0) when the stop condition is detected.
bit to 1), to forcibly disable detection.
2
C communications are already in progress
2
C operation is enabled (IICE0 = 1), the bus communication status (the IICBSY flag (bit 6 of the
2
C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
2
C communications. To avoid this, start I
2
C recognizes that the SDAA0 pin has gone low (detects a start
2
C in the following sequence.
CHAPTER 15 SERIAL INTERFACE IICA
2
C.
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