UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 692

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
22.4.1 When used as reset
(1) When detecting level of supply voltage (V
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(a) When LVI default start function stopped is set (LVISTART = 0)
• When starting operation
• When stopping operation
Write 00H to LVIM.
Clear LVIMD to 0 and then LVION to 0.
•
•
Either of the following procedures must be executed.
Cautions 1. Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after the
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Figure 22-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <7> above.
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for an operation stabilization time (10
Wait until it is checked that (supply voltage (V
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected).
(V
selection register (LVIS).
DD
2. If supply voltage (V
)) (default value).
processing in <4>.
reset signal is not generated.
DD
) ≥ LVI detection voltage (V
DD
)
DD
) ≥ LVI detection voltage (V
CHAPTER 22 LOW-VOLTAGE DETECTOR
μ
s (MAX.)).
LVI
) when LVIMD is set to 1, an internal
LVI
)) by bit 0 (LVIF) of LVIM.
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