UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 687

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Address: FFBEH
Symbol
Notes 1.
LVIM
2.
3.
4.
5.
LVISEL
LVION
LVION
LVIMD
<7>
The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVI resets (except resets by the LVI default start function).
The value of this register is reset to “00H” by other resets.
Bit 0 is read-only.
LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These are not
cleared to 0 in the case of an LVI reset.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for
an operation stabilization time (10
After the operation stabilizes, an external input (minimum pulse width: 200
required until LVIF is set (1) after the voltage drops to the LVI detection voltage or less.
78K0/KB2-L and 78K0/KC2-L only.
LVIF
0
1
0
1
0
1
0
1
Notes 3, 4
Notes 3, 5
After reset: 00H
Note 3
Disables operation
Enables operation
Detects level of supply voltage (V
Detects level of input voltage from external input pin (EXLVI)
• LVISEL = 0: Generates an internal interrupt signal when the supply voltage (V
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
• LVISEL = 0: Generates an internal reset signal when the supply voltage (V
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
• LVISEL = 0: Supply voltage (V
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ LVI detection voltage
• LVISEL = 0: Supply voltage (V
• LVISEL = 1: Input voltage from external input pin (EXLVI) < LVI detection voltage
Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
6
0
Note 1
Low-voltage detection operation mode (interrupt/reset) selection
lower than the LVI detection voltage (V
becomes V
input pin (EXLVI) drops lower than the LVI detection voltage (V
(EXLVI < V
V
LVI detection voltage (V
external input pin (EXLVI) < the LVI detection voltage (V
releases the reset signal when EXLVI ≥ V
is disabled
(V
(V
5
0
EXLVI
EXLVI
EXLVI
R/W
).
), or when LVI operation is disabled
)
Note 2
Enables low-voltage detection operation
LVI
EXLVI
μ
4
0
or higher (V
s (MAX.)) from when LVION is set to 1 until operation is stabilized.
) or when EXLVI becomes V
Voltage detection selection
Low-voltage detection flag
DD
DD
DD
) ≥ LVI detection voltage (V
) < LVI detection voltage (V
)
LVI
DD
) and releases the reset signal when V
3
0
≥ V
LVI
CHAPTER 22 LOW-VOLTAGE DETECTOR
).
LVISEL
<2>
LVI
) (V
EXLVI
Note 5
EXLVI
DD
.
LVI
LVI
< V
or higher (EXLVI ≥
), or when LVI operation
)
LVIMD
LVI
<1>
) or when V
EXLVI
) and
DD
μ
EXLVI
LVIF
s) of 200
) < the
<0>
DD
DD
DD
)
) drops
≥ V
LVI
.
μ
s or more is
673