UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 514
UPD78F0551MA-FAA-AX
Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0551MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Symbol
IICAF0
Address: FFA9H
Note Bits 6 and 7 are read-only.
Cautions 1. Write to the STCEN bit only when the operation is stopped (IICE0 = 0).
Remark
Condition for clearing (IICRSV = 0)
Condition for clearing (STCEN = 0)
Condition for clearing (STCF = 0)
Condition for clearing (IICBSY = 0)
IICBSY
STCEN
IICRSV
STCF
STCF
Cleared by instruction
Reset
Cleared by instruction
Detection of start condition
Reset
<7>
Cleared by STT0 = 1
When IICE0 = 0 (operation stop)
Reset
Detection of stop condition
When IICE0 = 0 (operation stop)
Reset
0
1
0
1
0
1
0
1
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status
3. Write to the IICRSV bit only when the operation is stopped (IICE0 = 0).
STT0: Bit 1 of IICA control register 0 (IICACTL0)
IICE0: Bit 7 of IICA control register 0 (IICACTL0)
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
Bus release status (communication initial status when STCEN = 1)
Bus communication status (communication initial status when STCEN = 0)
Enable communication reservation
Disable communication reservation
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
IICBSY
when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to
verify that no third party communications are in progress in order to prevent such
communications from being destroyed.
After reset: 00H
<6>
Figure 15-7. Format of IICA Flag Register 0 (IICAF0)
5
0
R/W
Communication reservation function disable bit
4
0
Note
3
0
Initial start enable trigger
I
2
C bus status flag
STT0 clear flag
Condition for setting (STCF = 1)
Condition for setting (IICBSY = 1)
Condition for setting (STCEN = 1)
Condition for setting (IICRSV = 1)
2
0
STT0 bit cleared to 0 when communication
reservation is disabled (IICRSV = 1).
Set by instruction
Generating start condition unsuccessful and the
Detection of start condition
Setting of the IICE0 bit when STCEN = 0
Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
STCEN
<1>
IICRSV
<0>
500
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