UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 474
UPD78F0551MA-FAA-AX
Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0551MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2-L
(5) Baud rate generator control register 6 (BRGC6)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Address: FF57H After reset: FFH R/W
BRGC6
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67
Remarks 1. f
Symbol
This register sets the division value of the 8-bit counter of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
2. The baud rate is the output clock of the 8-bit counter divided by 2.
2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255)
3. ×: Don’t care
MDL67
MDL67
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
7
0
0
0
0
•
•
•
•
•
1
1
1
1
to MDL60 bits.
XCLK6
Figure 14-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
MDL66
MDL66
: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
6
0
0
0
0
1
1
1
1
•
•
•
•
•
MDL65
MDL65
5
0
0
0
0
1
1
1
1
•
•
•
•
•
MDL64
MDL64
4
0
0
0
0
1
1
1
1
•
•
•
•
•
MDL63
MDL63
3
0
0
0
0
1
1
1
1
•
•
•
•
•
MDL62
MDL62
2
0
1
1
1
•
•
•
•
•
1
1
1
1
MDL61
MDL61
CHAPTER 14 SERIAL INTERFACE UART6
1
×
0
0
1
•
•
•
•
•
0
0
1
1
MDL60
MDL60
0
×
0
1
0
0
1
0
1
•
•
•
•
•
252
253
254
255
k
×
4
5
6
•
•
•
•
•
Setting prohibited
f
f
f
f
f
f
f
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
Output clock selection of
/4
/5
/6
/252
/253
/254
/255
8-bit counter
•
•
•
•
•
460
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