UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 531

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCLA0 is at low level while attempting to generate a
restart condition
Notes 1. When the WTIM0 bit (bit 3 of the IICA control register 0 (IICACTL0)) = 1, an interrupt request occurs at the
Remark
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
falling edge of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an
interrupt request occurs at the falling edge of the eighth clock.
SPIE0: Bit 4 of IICA control register 0 (IICACTL0)
Status During Arbitration
Table 15-4. Status During Arbitration and Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
CHAPTER 15 SERIAL INTERFACE IICA
Note 2
Note 2
Note 1
Note 1
Note 1
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